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path: root/target/riscv/cpu_bits.h
AgeCommit message (Expand)Author
2024-10-02target/riscv: Preliminary textra trigger CSR writting supportAlvin Chang
2024-07-18target/riscv: Add cycle & instret privilege mode filtering supportKaiwen Xue
2024-07-18target/riscv: Add cycle & instret privilege mode filtering definitionsKaiwen Xue
2024-06-26target/riscv: Reserve exception codes for sw-check and hw-errFea.Wang
2024-06-26target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32Fea.Wang
2024-06-26target/riscv: Add 'P1P13' bit in SMSTATEEN0Fea.Wang
2024-06-26target/riscv: Move Guest irqs out of the core local irqs range.Rajnesh Kanwal
2024-06-03target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63Clément Léger
2024-02-09target/riscv: FCSR doesn't contain vxrm and vxsatLIU Zhiwei
2024-02-09target/riscv: Implement optional CSR mcontext of debug Sdtrig extensionAlvin Chang
2023-11-07target/riscv: Add M-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal
2023-09-11target/riscv: Update CSR bits name for svadu extensionWeiwei Li
2023-09-08riscv: spelling fixesMichael Tokarev
2023-05-05riscv: Make sure an exception is raised if a pte is malformedAlexandre Ghiti
2023-05-05target/riscv: Add a general status enum for extensionsLIU Zhiwei
2023-05-05target/riscv: Use PRV_RESERVED instead of PRV_HWeiwei Li
2023-05-05target/riscv: Fix format for commentsWeiwei Li
2023-05-05target/riscv: Convert env->virt to a bool env->virt_enabledLIU Zhiwei
2023-05-05target/riscv: add support for Zcmt extensionWeiwei Li
2023-03-01target/riscv: Add csr support for svaduWeiwei Li
2023-01-06target/riscv: Add smstateen supportMayuresh Chitale
2022-09-27target/riscv: debug: Introduce tinfo CSRFrank Chang
2022-09-27target/riscv: Remove sideleg and sedelegRahul Pathak
2022-09-07target/riscv: Add sscofpmf extension supportAtish Patra
2022-09-07target/riscv: Add vstimecmp supportAtish Patra
2022-09-07target/riscv: Add stimecmp supportAtish Patra
2022-07-03target/riscv: Update default priority table for local interruptsAnup Patel
2022-07-03target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bitsAnup Patel
2022-07-03target/riscv: Implement mcountinhibit CSRAtish Patra
2022-04-29target/riscv: rvk: add CSR support for ZkrWeiwei Li
2022-04-22target/riscv: Add *envcfg* CSRs supportAtish Patra
2022-04-22target/riscv: Add support for mconfigptrAtish Patra
2022-02-16target/riscv: add support for svpbmt extensionWeiwei Li
2022-02-16target/riscv: add support for svnapot extensionWeiwei Li
2022-02-16target/riscv: Ignore reserved bits in PTE for RV64Guo Ren
2022-02-16target/riscv: Add defines for AIA CSRsAnup Patel
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel
2022-02-16target/riscv: Implement SGEIP bit in hip and hie CSRsAnup Patel
2022-01-21target/riscv: Enable uxl field writeLIU Zhiwei
2022-01-08target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot
2021-12-20target/riscv: rvv-1.0: add vlenb registerGreentime Hu
2021-12-20target/riscv: rvv-1.0: add vcsr registerLIU Zhiwei
2021-12-20target/riscv: rvv-1.0: add sstatus VS fieldLIU Zhiwei
2021-12-20target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei
2021-10-29target/riscv: remove force HS exceptionJose Martins
2021-10-28target/riscv: Add CSR defines for RISC-V PM extensionAlexey Baturo
2021-10-22target/riscv: Create RISCVMXL enumerationRichard Henderson
2021-10-22target/riscv: Remove some unused macrosAlistair Francis
2021-09-21target/riscv: csr: Rename HCOUNTEREN_CY and friendsBin Meng
2021-09-21target/riscv: Update the ePMP CSR addressAlistair Francis
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