aboutsummaryrefslogtreecommitdiff
path: root/target/riscv/cpu_bits.h
AgeCommit message (Expand)Author
2022-02-16target/riscv: add support for svpbmt extensionWeiwei Li
2022-02-16target/riscv: add support for svnapot extensionWeiwei Li
2022-02-16target/riscv: Ignore reserved bits in PTE for RV64Guo Ren
2022-02-16target/riscv: Add defines for AIA CSRsAnup Patel
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel
2022-02-16target/riscv: Implement SGEIP bit in hip and hie CSRsAnup Patel
2022-01-21target/riscv: Enable uxl field writeLIU Zhiwei
2022-01-08target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot
2021-12-20target/riscv: rvv-1.0: add vlenb registerGreentime Hu
2021-12-20target/riscv: rvv-1.0: add vcsr registerLIU Zhiwei
2021-12-20target/riscv: rvv-1.0: add sstatus VS fieldLIU Zhiwei
2021-12-20target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei
2021-10-29target/riscv: remove force HS exceptionJose Martins
2021-10-28target/riscv: Add CSR defines for RISC-V PM extensionAlexey Baturo
2021-10-22target/riscv: Create RISCVMXL enumerationRichard Henderson
2021-10-22target/riscv: Remove some unused macrosAlistair Francis
2021-09-21target/riscv: csr: Rename HCOUNTEREN_CY and friendsBin Meng
2021-09-21target/riscv: Update the ePMP CSR addressAlistair Francis
2021-06-08target/riscv: fix wfi exception behaviorJose Martins
2021-05-11target/riscv: Remove the unused HSTATUS_WPRI macroAlistair Francis
2021-05-11target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis
2021-05-11target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis
2021-05-11target/riscv: Remove the hardcoded HGATP_MODE macroAlistair Francis
2021-05-11target/riscv: Remove the hardcoded SSTATUS_SD macroAlistair Francis
2021-05-11target/riscv: Define ePMP mseccfgHou Weiying
2021-05-11target/riscv: Convert the RISC-V exceptions to an enumAlistair Francis
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra
2021-03-04target-riscv: support QMP dump-guest-memoryYifei Jiang
2021-01-18riscv: Add semihosting supportKeith Packard
2020-12-17target/riscv: csr: Remove compile time XLEN checksAlistair Francis
2020-12-17target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSRAlex Richardson
2020-11-09target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang
2020-08-25target/riscv: Support the Virtual Instruction faultAlistair Francis
2020-08-25target/riscv: Support the v0.6 Hypervisor extension CRSsAlistair Francis
2020-08-25target/riscv: Update the CSRs to the v0.6 Hyp extensionAlistair Francis
2020-08-25target/riscv: Update the Hypervisor trap return/entryAlistair Francis
2020-08-25target/riscv: Convert MSTATUS MTL to GVAAlistair Francis
2020-08-25target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis
2020-08-25target/riscv: Allow setting a two-stage lookup in the virt statusAlistair Francis
2020-07-02target/riscv: support vector extension csrLIU Zhiwei
2020-02-27target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis
2020-02-27target/riscv: Add virtual register swapping functionAlistair Francis
2020-02-27target/riscv: Add the force HS exception modeAlistair Francis
2020-02-27target/riscv: Add the virtulisation modeAlistair Francis
2020-02-27target/riscv: Rename the H irqs to VS irqsAlistair Francis
2020-02-27target/riscv: Add support for the new execption numbersAlistair Francis
2020-02-27target/riscv: Add the Hypervisor CSRs to CPUStateAlistair Francis
2019-09-17target/riscv: Update the Hypervisor CSRs to v0.4Alistair Francis
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-01 05:38:55 +0000