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QEMU is a generic and open source machine & userspace emulator and virtualizer
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riscv
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cpu_bits.h
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Author
2021-06-08
target/riscv: fix wfi exception behavior
Jose Martins
2021-05-11
target/riscv: Remove the unused HSTATUS_WPRI macro
Alistair Francis
2021-05-11
target/riscv: Remove the hardcoded SATP_MODE macro
Alistair Francis
2021-05-11
target/riscv: Remove the hardcoded MSTATUS_SD macro
Alistair Francis
2021-05-11
target/riscv: Remove the hardcoded HGATP_MODE macro
Alistair Francis
2021-05-11
target/riscv: Remove the hardcoded SSTATUS_SD macro
Alistair Francis
2021-05-11
target/riscv: Define ePMP mseccfg
Hou Weiying
2021-05-11
target/riscv: Convert the RISC-V exceptions to an enum
Alistair Francis
2021-05-11
target/riscv: Remove privilege v1.9 specific CSR related code
Atish Patra
2021-03-04
target-riscv: support QMP dump-guest-memory
Yifei Jiang
2021-01-18
riscv: Add semihosting support
Keith Packard
2020-12-17
target/riscv: csr: Remove compile time XLEN checks
Alistair Francis
2020-12-17
target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
Alex Richardson
2020-11-09
target/riscv: Remove the HS_TWO_STAGE flag
Alistair Francis
2020-11-03
target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
Yifei Jiang
2020-08-25
target/riscv: Support the Virtual Instruction fault
Alistair Francis
2020-08-25
target/riscv: Support the v0.6 Hypervisor extension CRSs
Alistair Francis
2020-08-25
target/riscv: Update the CSRs to the v0.6 Hyp extension
Alistair Francis
2020-08-25
target/riscv: Update the Hypervisor trap return/entry
Alistair Francis
2020-08-25
target/riscv: Convert MSTATUS MTL to GVA
Alistair Francis
2020-08-25
target/riscv: Allow generating hlv/hlvx/hsv instructions
Alistair Francis
2020-08-25
target/riscv: Allow setting a two-stage lookup in the virt status
Alistair Francis
2020-07-02
target/riscv: support vector extension csr
LIU Zhiwei
2020-02-27
target/riscv: Add the MSTATUS_MPV_ISSET helper macro
Alistair Francis
2020-02-27
target/riscv: Add support for the 32-bit MSTATUSH CSR
Alistair Francis
2020-02-27
target/riscv: Add virtual register swapping function
Alistair Francis
2020-02-27
target/riscv: Add the force HS exception mode
Alistair Francis
2020-02-27
target/riscv: Add the virtulisation mode
Alistair Francis
2020-02-27
target/riscv: Rename the H irqs to VS irqs
Alistair Francis
2020-02-27
target/riscv: Add support for the new execption numbers
Alistair Francis
2020-02-27
target/riscv: Add the Hypervisor CSRs to CPUState
Alistair Francis
2019-09-17
target/riscv: Update the Hypervisor CSRs to v0.4
Alistair Francis
2019-06-25
target/riscv: Add the mcountinhibit CSR
Alistair Francis
2019-06-12
Supply missing header guards
Markus Armbruster
2019-05-24
target/riscv: Add the HGATP register masks
Alistair Francis
2019-05-24
target/riscv: Add the HSTATUS register masks
Alistair Francis
2019-05-24
target/riscv: Add Hypervisor CSR macros
Alistair Francis
2019-05-24
target/riscv: Add the MPV and MTL mstatus bits
Alistair Francis
2019-05-24
target/riscv: Mark privilege level 2 as reserved
Alistair Francis
2019-03-19
RISC-V: Fixes to CSR_* register macros.
Jim Wilson
2019-02-11
RISC-V: Add misa runtime write support
Michael Clark
2018-10-17
RISC-V: Update CSR and interrupt definitions
Michael Clark
2018-09-04
RISC-V: Improve page table walker spec compliance
Michael Clark
2018-03-07
RISC-V CPU Core Definition
Michael Clark