slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2024-07-18	target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR	Yu-Ming Chang
2024-07-18	target/riscv: Save counter values during countinhibit update	Atish Patra
2024-07-18	target/riscv: Implement privilege mode filtering for cycle/instret	Atish Patra
2024-07-18	target/riscv: Add cycle & instret privilege mode filtering definitions	Kaiwen Xue
2024-07-18	target/riscv: Combine set_mode and set_virt functions.	Rajnesh Kanwal
2024-06-26	target/riscv: Introduce extension implied rules definition	Frank Chang
2024-06-26	target/riscv: Define macros and variables for ss1p13	Fea.Wang
2024-06-26	target/riscv: Reuse the conversion function of priv_spec	Jim Shu
2024-06-04	Merge tag 'hw-misc-accel-20240604' of https://github.com/philmd/qemu into sta...	Richard Henderson
2024-06-04	target/riscv: Restrict riscv_cpu_do_interrupt() to sysemu	Philippe Mathieu-Daudé
2024-06-03	riscv: thead: Add th.sxstatus CSR emulation	Christoph Müllner
2024-06-03	target/riscv: Implement dynamic establishment of custom decoder	Huang Tao
2024-06-03	target/riscv/kvm: Fix exposure of Zkr	Andrew Jones
2024-04-26	target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h'	Philippe Mathieu-Daudé
2024-03-08	target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit	Vadim Shakirov
2024-02-28	target/riscv: Use GDBFeature for dynamic XML	Akihiko Odaki
2024-02-09	target/riscv: support new isa extension detection devicetree properties	Conor Dooley
2024-02-09	target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG...	Conor Dooley
2024-02-09	target/riscv: Move misa_mxl_max to class	Akihiko Odaki
2024-02-09	target/riscv: change vext_get_vlmax() arguments	Daniel Henrique Barboza
2024-02-09	target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax()	Daniel Henrique Barboza
2024-02-09	target/riscv: Implement optional CSR mcontext of debug Sdtrig extension	Alvin Chang
2024-02-09	target/riscv: remove riscv_cpu_options[]	Daniel Henrique Barboza
2024-02-09	target/riscv: create finalize_features() for KVM	Daniel Henrique Barboza
2024-02-09	target/riscv: rework 'vext_spec'	Daniel Henrique Barboza
2024-02-09	target/riscv: rework 'priv_spec'	Daniel Henrique Barboza
2024-02-09	target/riscv: make riscv_cpu_is_vendor() public	Daniel Henrique Barboza
2024-02-09	target/riscv/cpu_cfg.h: remove unused fields	Daniel Henrique Barboza
2024-02-09	target/riscv: Add infrastructure for 'B' MISA extension	Rob Bradford
2024-02-03	include/exec: Implement cpu_mmu_index generically	Richard Henderson
2024-02-03	target/riscv: Rename riscv_cpu_mmu_index to riscv_env_mmu_index	Richard Henderson
2024-01-10	target/riscv: add 'parent' in profile description	Daniel Henrique Barboza
2024-01-10	target/riscv: add satp_mode profile support	Daniel Henrique Barboza
2024-01-10	target/riscv/cpu.c: add riscv_cpu_is_32bit()	Daniel Henrique Barboza
2024-01-10	target/riscv: add priv ver restriction to profiles	Daniel Henrique Barboza
2024-01-10	target/riscv: add rva22u64 profile definition	Daniel Henrique Barboza
2024-01-10	target/riscv/tcg: add 'zic64b' support	Daniel Henrique Barboza
2024-01-05	target/riscv: Use generic cpu_list()	Gavin Shan
2023-11-15	target/riscv/cpu.h: spelling fix: separatly	Michael Tokarev
2023-11-07	target: Move ArchCPUClass definition to 'cpu.h'	Philippe Mathieu-Daudé
2023-11-07	target/riscv: Move TYPE_RISCV_CPU_BASE definition to 'cpu.h'	Philippe Mathieu-Daudé
2023-11-07	target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'	Philippe Mathieu-Daudé
2023-11-07	target: Unify QOM style	Philippe Mathieu-Daudé
2023-11-07	target/riscv: add riscv_cpu_accelerator_compatible()	Daniel Henrique Barboza
2023-11-07	target/riscv/tcg: add tcg_cpu_finalize_features()	Daniel Henrique Barboza
2023-11-07	target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.	Rajnesh Kanwal
2023-11-07	target/riscv: Add M-mode virtual interrupt and IRQ filtering support.	Rajnesh Kanwal
2023-11-07	target/riscv: Split interrupt logic from riscv_cpu_update_mip.	Rajnesh Kanwal
2023-10-12	target/riscv: deprecate capital 'Z' CPU properties	Daniel Henrique Barboza
2023-10-12	target/riscv: add riscv_cpu_get_name()	Daniel Henrique Barboza