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path: root/target/riscv/cpu.h
AgeCommit message (Expand)Author
2023-07-10target/riscv/cpu: add misa_ext_info_arr[]Daniel Henrique Barboza
2023-07-10target/riscv: Add additional xlen for address when MPRV=1Weiwei Li
2023-06-28target/riscv: Restrict KVM-specific fields from ArchCPUPhilippe Mathieu-Daudé
2023-06-26target: Widen pc/cs_base in cpu_get_tb_cpu_stateAnton Johansson
2023-06-13target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.hWeiwei Li
2023-06-13target/riscv: rework write_misa()Daniel Henrique Barboza
2023-06-13target/riscv: add PRIV_VERSION_LATESTDaniel Henrique Barboza
2023-05-05target/riscv: add CPU QOM headerDaniel Henrique Barboza
2023-05-05target/riscv: Introduce mmuidx_2stageRichard Henderson
2023-05-05target/riscv: Handle HLV, HSV via helpersRichard Henderson
2023-05-05target/riscv: Reduce overhead of MSTATUS_SUM changeFei Wu
2023-05-05target/riscv: Separate priv from mmu_idxFei Wu
2023-05-05target/riscv: Add a tb flags field for vstartLIU Zhiwei
2023-05-05target/riscv: Remove mstatus_hs_{fs, vs} from tb_flagsRichard Henderson
2023-05-05target/riscv: Encode the FS and VS on a normal way for tb flagsLIU Zhiwei
2023-05-05target/riscv: Add a general status enum for extensionsLIU Zhiwei
2023-05-05target/riscv: Extract virt enabled state from tb flagsLIU Zhiwei
2023-05-05target/riscv: Use PRV_RESERVED instead of PRV_HWeiwei Li
2023-05-05target/riscv/cpu.c: redesign register_cpu_props()Daniel Henrique Barboza
2023-05-05target/riscv: add RVG and remove cpu->cfg.ext_gDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_vDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_jDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_hDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_uDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_sDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_mDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_eDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_iDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_fDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_dDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_cDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_aDaniel Henrique Barboza
2023-05-05target/riscv: Fix lines with over 80 charactersWeiwei Li
2023-05-05target/riscv: Fix format for commentsWeiwei Li
2023-05-05target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li
2023-05-05target/riscv: Convert env->virt to a bool env->virt_enabledLIU Zhiwei
2023-05-05target/riscv: Add support for ZceWeiwei Li
2023-05-05target/riscv: add support for Zcmt extensionWeiwei Li
2023-05-05target/riscv: add cfg properties for Zc* extensionWeiwei Li
2023-05-05target/riscv: Simplify type conversion for CPURISCVStateWeiwei Li
2023-03-06riscv: Introduce satp mode hw capabilitiesAlexandre Ghiti
2023-03-06riscv: Allow user to set the satp modeAlexandre Ghiti
2023-03-05target/riscv: implement Zicbom extensionChristoph Muellner
2023-03-05target/riscv: implement Zicboz extensionChristoph Muellner
2023-03-01Merge patch series "target/riscv: Add support for Svadu extension"Palmer Dabbelt
2023-03-01target/riscv: Add csr support for svaduWeiwei Li
2023-03-01target/riscv: Add support for Zicond extensionWeiwei Li
2023-03-01Merge patch series "target/riscv: Some updates to float point related extensi...Palmer Dabbelt
2023-03-01target/riscv: Add cfg properties for Zv* extensionsWeiwei Li
2023-03-01target/riscv/cpu: remove CPUArchState::features and friendsDaniel Henrique Barboza
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