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QEMU is a generic and open source machine & userspace emulator and virtualizer
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cpu.h
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Author
2020-07-13
target/riscv: fix vill bit index in vtype register
Frank Chang
2020-07-02
target/riscv: configure and turn on vector extension from command line
LIU Zhiwei
2020-07-02
target/riscv: add vector configure instruction
LIU Zhiwei
2020-07-02
target/riscv: implementation-defined constant parameters
LIU Zhiwei
2020-07-02
target/riscv: add vector extension field in CPURISCVState
LIU Zhiwei
2020-06-03
target/riscv: Add the lowRISC Ibex CPU
Alistair Francis
2020-06-03
target/riscv: Drop support for ISA spec version 1.09.1
Alistair Francis
2020-06-03
target/riscv: Remove the deprecated CPUs
Alistair Francis
2020-04-29
target/riscv: Add a sifive-e34 cpu type
Corey Wharton
2020-03-19
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...
Peter Maydell
2020-03-17
cpu: Use DeviceClass reset instead of a special CPUClass reset
Peter Maydell
2020-03-17
gdbstub: extend GByteArray to read register helpers
Alex Bennée
2020-02-27
target/riscv: Emulate TIME CSRs for privileged mode
Anup Patel
2020-02-27
target/riscv: Allow enabling the Hypervisor extension
Alistair Francis
2020-02-27
target/riscv: Add support for the 32-bit MSTATUSH CSR
Alistair Francis
2020-02-27
target/riscv: Implement second stage MMU
Alistair Francis
2020-02-27
target/riscv: Only set TB flags with FP status if enabled
Alistair Francis
2020-02-27
target/riscv: Add virtual register swapping function
Alistair Francis
2020-02-27
target/riscv: Add the force HS exception mode
Alistair Francis
2020-02-27
target/riscv: Add the virtulisation mode
Alistair Francis
2020-02-27
target/riscv: Add the Hypervisor CSRs to CPUState
Alistair Francis
2020-02-27
target/riscv: Add the Hypervisor extension
Alistair Francis
2020-02-27
target/riscv: Convert MIP CSR to target_ulong
Alistair Francis
2020-01-16
target/riscv: Fix tb->flags FS status
ShihPo Hung
2019-11-14
target/riscv: Remove atomic accesses to MIP CSR
Alistair Francis
2019-10-28
RISC-V: Implement cpu_do_transaction_failed
Palmer Dabbelt
2019-09-17
target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point
Alistair Francis
2019-09-17
target/riscv: Create function to test if FP is enabled
Alistair Francis
2019-08-21
hw/core: Move cpu.c, cpu.h from qom/ to hw/core/
Markus Armbruster
2019-08-19
target/riscv: rationalise softfloat includes
Alex Bennée
2019-06-25
RISC-V: Add support for the Zicsr extension
Palmer Dabbelt
2019-06-25
RISC-V: Add support for the Zifencei extension
Palmer Dabbelt
2019-06-25
target/riscv: Add support for disabling/enabling Counters
Alistair Francis
2019-06-25
target/riscv: Remove user version information
Alistair Francis
2019-06-24
target/riscv: Add the privledge spec version 1.11.0
Alistair Francis
2019-06-24
target/riscv: Restructure deprecatd CPUs
Alistair Francis
2019-06-23
RISC-V: Check PMP during Page Table Walks
Hesham Almatary
2019-06-23
target/riscv: Implement riscv_cpu_unassigned_access
Michael Clark
2019-06-23
target/riscv: Allow setting ISA extensions via CPU props
Alistair Francis
2019-06-12
Include qemu-common.h exactly where needed
Markus Armbruster
2019-06-10
cpu: Remove CPU_COMMON
Richard Henderson
2019-06-10
cpu: Introduce CPUNegativeOffsetState
Richard Henderson
2019-06-10
cpu: Move ENV_OFFSET to exec/gen-icount.h
Richard Henderson
2019-06-10
target/riscv: Use env_cpu, env_archcpu
Richard Henderson
2019-06-10
cpu: Replace ENV_GET_CPU with env_cpu
Richard Henderson
2019-06-10
cpu: Define ArchCPU
Richard Henderson
2019-06-10
cpu: Define CPUArchState with typedef
Richard Henderson
2019-06-10
tcg: Split out target/arch/cpu-param.h
Richard Henderson
2019-05-24
target/riscv: Add a base 32 and 64 bit CPU
Alistair Francis
2019-05-24
target/riscv: Create settable CPU properties
Alistair Francis
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