Age | Commit message (Expand) | Author |
2021-03-22 | target/riscv: Add proper two-stage lookup exception detection | Georg Kotheimer |
2021-03-09 | Various spelling fixes | Michael Tokarev |
2021-03-04 | target-riscv: support QMP dump-guest-memory | Yifei Jiang |
2021-02-05 | cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass | Claudio Fontana |
2021-02-05 | cpu: move do_unaligned_access to tcg_ops | Claudio Fontana |
2021-02-05 | cpu: move cc->transaction_failed to tcg_ops | Claudio Fontana |
2021-02-05 | cpu: move cc->do_interrupt to tcg_ops | Claudio Fontana |
2021-02-05 | cpu: Move tlb_fill to tcg_ops | Eduardo Habkost |
2021-02-05 | cpu: Move cpu_exec_* to tcg_ops | Eduardo Habkost |
2021-02-05 | cpu: Move synchronize_from_tb() to tcg_ops | Eduardo Habkost |
2021-02-05 | target/riscv: remove CONFIG_TCG, as it is always TCG | Claudio Fontana |
2021-02-05 | cpu: Introduce TCGCpuOperations struct | Eduardo Habkost |
2021-01-16 | target/riscv: Generate the GDB XML file for CSR registers dynamically | Bin Meng |
2021-01-16 | gdb: riscv: Add target description | Sylvain Pelissier |
2021-01-07 | tcg: Make tb arg to synchronize_from_tb const | Richard Henderson |
2020-12-17 | target/riscv: cpu: Set XLEN independently from target | Alistair Francis |
2020-12-17 | target/riscv: cpu: Remove compile time XLEN checks | Alistair Francis |
2020-12-17 | target/riscv: Specify the XLEN for CPUs | Alistair Francis |
2020-12-17 | target/riscv: Add a riscv_cpu_is_32bit() helper function | Alistair Francis |
2020-11-03 | target/riscv: Add basic vmstate description of CPU | Yifei Jiang |
2020-11-03 | target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit | Yifei Jiang |
2020-09-18 | target/riscv: Set instance_align on RISCVCPU TypeInfo | Richard Henderson |
2020-09-09 | target/riscv: cpu: Set reset vector based on the configured property value | Bin Meng |
2020-09-09 | target/riscv: cpu: Add a new 'resetvec' property | Bin Meng |
2020-09-09 | target/riscv: Fix bug in getting trap cause name for trace_riscv_trap | Yifei Jiang |
2020-07-02 | target/riscv: configure and turn on vector extension from command line | LIU Zhiwei |
2020-07-02 | target/riscv: implementation-defined constant parameters | LIU Zhiwei |
2020-06-19 | hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 | Bin Meng |
2020-06-19 | target/riscv: Rename IBEX CPU init routine | Bin Meng |
2020-06-19 | riscv: Keep the CPU init routine names consistent | Bin Meng |
2020-06-19 | riscv: Generalize CPU init routine for the imacu CPU | Bin Meng |
2020-06-19 | riscv: Generalize CPU init routine for the gcsu CPU | Bin Meng |
2020-06-19 | riscv: Generalize CPU init routine for the base CPU | Bin Meng |
2020-06-08 | Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.1-pull-re... | Peter Maydell |
2020-06-05 | target/riscv/cpu: Restrict CPU migration to system-mode | Philippe Mathieu-Daudé |
2020-06-03 | target/riscv: Add the lowRISC Ibex CPU | Alistair Francis |
2020-06-03 | target/riscv: Don't set PMP feature in the cpu init | Alistair Francis |
2020-06-03 | target/riscv: Disable the MMU correctly | Alistair Francis |
2020-06-03 | target/riscv: Don't overwrite the reset vector | Alistair Francis |
2020-06-03 | target/riscv: Drop support for ISA spec version 1.09.1 | Alistair Francis |
2020-06-03 | target/riscv: Remove the deprecated CPUs | Alistair Francis |
2020-04-29 | target/riscv: Add a sifive-e34 cpu type | Corey Wharton |
2020-03-17 | cpu: Use DeviceClass reset instead of a special CPUClass reset | Peter Maydell |
2020-03-05 | RISC-V: Add a missing "," in riscv_excp_names | Palmer Dabbelt |
2020-02-27 | target/riscv: Allow enabling the Hypervisor extension | Alistair Francis |
2020-02-27 | target/riscv: Add support for the 32-bit MSTATUSH CSR | Alistair Francis |
2020-02-27 | target/riscv: Dump Hypervisor registers if enabled | Alistair Francis |
2020-02-27 | target/riscv: Rename the H irqs to VS irqs | Alistair Francis |
2020-02-27 | target/riscv: Add support for the new execption numbers | Alistair Francis |
2020-02-27 | target/riscv: Convert MIP CSR to target_ulong | Alistair Francis |