slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2021-07-13	target/openrisc: Use dc->zero in gen_add, gen_addc	Richard Henderson
2021-07-13	target/openrisc: Cache constant 0 in DisasContext	Richard Henderson
2021-07-13	target/openrisc: Use tcg_constant_tl for dc->R0	Richard Henderson
2021-07-13	target/openrisc: Use tcg_constant_*	Richard Henderson
2021-07-12	Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' into...	Peter Maydell
2021-07-09	target/openrisc: Use translator_use_goto_tb	Richard Henderson
2021-07-09	tcg: Avoid including 'trace-tcg.h' in target translate.c	Philippe Mathieu-Daudé
2021-07-09	meson: Introduce target-specific Kconfig	Philippe Mathieu-Daudé
2021-05-26	hw/core: Constify TCGCPUOps	Richard Henderson
2021-05-26	cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps	Philippe Mathieu-Daudé
2021-05-26	cpu: Introduce SysemuCPUOps structure	Philippe Mathieu-Daudé
2021-05-02	Do not include sysemu/sysemu.h if it's not really necessary	Thomas Huth
2021-04-01	target/openrisc: fix icount handling for timer instructions	Pavel Dovgalyuk
2021-02-05	cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass	Claudio Fontana
2021-02-05	cpu: move cc->do_interrupt to tcg_ops	Claudio Fontana
2021-02-05	cpu: Move tlb_fill to tcg_ops	Eduardo Habkost
2021-02-05	cpu: Move cpu_exec_* to tcg_ops	Eduardo Habkost
2021-02-05	cpu: Introduce TCGCpuOperations struct	Eduardo Habkost
2020-12-19	migration: Replace migration's JSON writer by the general one	Markus Armbruster
2020-12-15	target/openrisc: Move pic_cpu code into CPU object proper	Peter Maydell
2020-11-17	target/openrisc: Remove dead code attempting to check "is timer disabled"	Peter Maydell
2020-09-18	qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros	Eduardo Habkost
2020-09-09	Use OBJECT_DECLARE_TYPE where possible	Eduardo Habkost
2020-09-09	Use DECLARE_CHECKER macros	Eduardo Habkost
2020-09-09	Move QOM typedefs and add missing includes	Eduardo Habkost
2020-08-21	meson: target	Paolo Bonzini
2020-08-21	meson: rename included C source files to .c.inc	Paolo Bonzini
2020-05-19	softfloat: Name compare relation enum	Richard Henderson
2020-03-19	Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...	Peter Maydell
2020-03-17	cpu: Use DeviceClass reset instead of a special CPUClass reset	Peter Maydell
2020-03-17	gdbstub: extend GByteArray to read register helpers	Alex Bennée
2020-01-24	cpu: Use cpu_class_set_parent_reset()	Greg Kurz
2020-01-17	Merge remote-tracking branch 'remotes/rth/tags/pull-or1k-20200116' into staging	Peter Maydell
2020-01-16	target/openrisc: Fix FPCSR mask to allow setting DZF	Stafford Horne
2020-01-15	tcg: Search includes from the project root source directory	Philippe Mathieu-Daudé
2019-10-28	target/openrisc: fetch code with translator_ld	Emilio G. Cota
2019-09-04	target/openrisc: Update cpu "any" to v1.3	Richard Henderson
2019-09-04	target/openrisc: Implement l.adrp	Richard Henderson
2019-09-04	target/openrisc: Implement move to/from FPCSR	Richard Henderson
2019-09-04	target/openrisc: Implement unordered fp comparisons	Richard Henderson
2019-09-04	target/openrisc: Add support for ORFPX64A32	Richard Henderson
2019-09-04	target/openrisc: Check CPUCFG_OF32S for float insns	Richard Henderson
2019-09-04	target/openrisc: Fix lf.ftoi.s	Richard Henderson
2019-09-04	target/openrisc: Add VR2 and AVR special processor registers	Richard Henderson
2019-09-04	target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init	Richard Henderson
2019-09-04	target/openrisc: Make VR and PPC read-only	Richard Henderson
2019-09-04	target/openrisc: Cache R0 in DisasContext	Richard Henderson
2019-09-04	target/openrisc: Replace cpu register array with a function	Richard Henderson
2019-09-04	target/openrisc: Add DisasContext parameter to check_r0_write	Richard Henderson
2019-09-03	tcg: TCGMemOp is now accelerator independent MemOp	Tony Nguyen