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path: root/target/openrisc/translate.c
AgeCommit message (Expand)Author
2018-05-09target/openrisc: convert to TranslatorOpsEmilio G. Cota
2018-05-09target/openrisc: convert to DisasContextBaseEmilio G. Cota
2017-10-27Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell
2017-10-25disas: Remove unused flags argumentsRichard Henderson
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota
2017-09-06target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova
2017-05-04target/openrisc: implement shadow registersStafford Horne
2017-02-14target/openrisc: Optimize for r0 being zeroRichard Henderson
2017-02-14target/openrisc: Tidy handling of delayed branchesRichard Henderson
2017-02-14target/openrisc: Tidy ppc/npc implementationRichard Henderson
2017-02-14target/openrisc: Optimize l.jal to nextRichard Henderson
2017-02-14target/openrisc: Fix maddRichard Henderson
2017-02-14target/openrisc: Implement muld, muldu, macu, msbuRichard Henderson
2017-02-14target/openrisc: Represent MACHI:MACLO as a single unitRichard Henderson
2017-02-14target/openrisc: Implement msyncRichard Henderson
2017-02-14target/openrisc: Enable trap, csync, msync, psync for user modeRichard Henderson
2017-02-14target/openrisc: Use movcond where appropriateRichard Henderson
2017-02-14target/openrisc: Keep SR_CY and SR_OV in a separate variablesRichard Henderson
2017-02-14target/openrisc: Keep SR_F in a separate variableRichard Henderson
2017-02-14target/openrisc: Invert the decoding in dec_calcRichard Henderson
2017-02-14target/openrisc: Put SR[OVE] in TB flagsRichard Henderson
2017-02-14target/openrisc: Streamline arithmetic and OVERichard Henderson
2017-02-14target/openrisc: Rationalize immediate extractionRichard Henderson
2017-02-14target/openrisc: Tidy insn dumpingRichard Henderson
2017-02-14target/openrisc: Implement lwa, swaRichard Henderson
2017-01-10target-openrisc: Use clz and ctz opcodesRichard Henderson
2016-12-20Move target-* CPU file into a target/ folderThomas Huth