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path: root/target/openrisc/cpu.h
AgeCommit message (Expand)Author
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster
2019-06-10cpu: Remove CPU_COMMONRichard Henderson
2019-06-10cpu: Introduce CPUNegativeOffsetStateRichard Henderson
2019-06-10cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson
2019-06-10target/openrisc: Use env_cpu, env_archcpuRichard Henderson
2019-06-10cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson
2019-06-10cpu: Define ArchCPURichard Henderson
2019-06-10cpu: Define CPUArchState with typedefRichard Henderson
2019-06-10tcg: Split out target/arch/cpu-param.hRichard Henderson
2019-05-10target/openrisc: Convert to CPUClass::tlb_fillRichard Henderson
2019-05-08target/openrisc: Fix LGPL information in the file headersThomas Huth
2019-04-18qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster
2019-04-18target: Simplify how the TARGET_cpu_list() printMarkus Armbruster
2018-07-03target/openrisc: Reorg tlb lookupRichard Henderson
2018-07-03target/openrisc: Increase the TLB sizeRichard Henderson
2018-07-03target/openrisc: Use identical sizes for ITLB and DTLBRichard Henderson
2018-07-03target/openrisc: Fix cpu_mmu_indexRichard Henderson
2018-07-03target/openrisc: Reduce tlb to a single dimensionRichard Henderson
2018-07-03target/openrisc: Remove indirect function calls for mmuRichard Henderson
2018-07-03target/openrisc: Merge tlb allocation into CPUOpenRISCStateRichard Henderson
2018-07-03target/openrisc: Add print_insn_or1kRichard Henderson
2018-03-19cpu: get rid of unused cpu_init() definesIgor Mammedov
2018-03-19cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov
2018-02-21target/*/cpu.h: remove softfloat.hAlex Bennée
2018-01-25accel/tcg: add size paremeter in tlb_fill()Laurent Vivier
2017-10-27openrisc: cleanup cpu type name compositionIgor Mammedov
2017-10-21openrisc/cputimer: Perparation for MulticoreStafford Horne
2017-09-01openrisc: replace cpu_openrisc_init() with cpu_generic_init()Igor Mammedov
2017-05-04target/openrisc: Support non-busy idle state using PMR SPRStafford Horne
2017-05-04target/openrisc: Remove duplicate features propertyStafford Horne
2017-05-04target/openrisc: implement shadow registersStafford Horne
2017-04-21target/openrisc: Implement EVBAR registerTim 'mithro' Ansell
2017-02-14target/openrisc: Optimize for r0 being zeroRichard Henderson
2017-02-14target/openrisc: Tidy handling of delayed branchesRichard Henderson
2017-02-14target/openrisc: Tidy ppc/npc implementationRichard Henderson
2017-02-14target/openrisc: Fix maddRichard Henderson
2017-02-14target/openrisc: Represent MACHI:MACLO as a single unitRichard Henderson
2017-02-14target/openrisc: Keep SR_CY and SR_OV in a separate variablesRichard Henderson
2017-02-14target/openrisc: Keep SR_F in a separate variableRichard Henderson
2017-02-14target/openrisc: Put SR[OVE] in TB flagsRichard Henderson
2017-02-14target/openrisc: Implement lwa, swaRichard Henderson
2017-02-14target/openrisc: Rename the cpu from or32 to or1kRichard Henderson
2017-01-13qom/cpu: move tlb_flush to cpu_common_resetAlex Bennée
2016-12-20Move target-* CPU file into a target/ folderThomas Huth