Age | Commit message (Expand) | Author |
---|---|---|
2017-06-05 | target/mips: optimize indirect branches | Aurelien Jarno |
2017-06-05 | target/mips: optimize cross-page direct jumps in softmmu | Aurelien Jarno |
2017-03-20 | target/mips: fix delay slot detection in gen_msa_branch() | Yongbok Kim |
2017-03-20 | target-mips: replace few LOG_DISAS() with trace points | Philippe Mathieu-Daudé |
2017-03-20 | target-mips: replace break by goto cp0_unimplemented | Philippe Mathieu-Daudé |
2017-03-20 | target-mips: log bad coprocessor0 register accesses with LOG_UNIMP | Philippe Mathieu-Daudé |
2017-03-20 | target-mips: remove old & unuseful comments | Philippe Mathieu-Daudé |
2017-02-21 | target-mips: Provide function to test if a CPU supports an ISA | Paul Burton |
2017-01-10 | target-mips: Use clz opcode | Richard Henderson |
2017-01-10 | target-mips: Use the new extract op | Richard Henderson |
2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth |