Age | Commit message (Expand) | Author |
---|---|---|
2022-11-08 | target/mips: Disable DSP ASE for Octeon68XX | Jiaxun Yang |
2022-07-12 | target/mips: introduce Cavium Octeon CPU model | Pavel Dovgalyuk |
2021-11-02 | target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU | Philippe Mathieu-Daudé |
2021-11-02 | target/mips: Fix Loongson-3A4000 MSAIR config register | Philippe Mathieu-Daudé |
2021-08-25 | target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr | Philippe Mathieu-Daudé |
2021-08-25 | target/mips: Document Loongson-3A CPU definitions | Philippe Mathieu-Daudé |
2021-01-14 | target/mips: Remove vendor specific CPU definitions | Philippe Mathieu-Daudé |
2021-01-14 | target/mips: Remove CPU_NANOMIPS32 definition | Philippe Mathieu-Daudé |
2021-01-14 | target/mips: Move msa_reset() to msa_helper.c | Philippe Mathieu-Daudé |
2021-01-14 | target/mips: Remove now unused ASE_MSA definition | Philippe Mathieu-Daudé |
2021-01-14 | target/mips: Simplify msa_reset() | Philippe Mathieu-Daudé |
2021-01-14 | target/mips: Rename translate_init.c as cpu-defs.c | Philippe Mathieu-Daudé |