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path: root/target/loongarch/insn_trans/trans_privileged.c.inc
AgeCommit message (Expand)Author
2024-01-06target/loongarch: move translate modules to tcg/Song Gao
2023-10-03tcg: Rename cpu_env to tcg_envRichard Henderson
2023-08-24target/loongarch: Add avail_IOCSR to check iocsr instructionsSong Gao
2023-08-24target/loongarch: Add avail_LSPW to check LSPW instructionsSong Gao
2023-08-24target/loongarch: Add a check parameter to the TRANS macroSong Gao
2023-07-24target/loongarch: Fix the CSRRD CPUID instruction on big endian hostsThomas Huth
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson
2023-03-05target/loongarch: Drop tcg_temp_freeRichard Henderson
2023-03-05target/loongarch: Drop temp_newRichard Henderson
2022-11-07target/loongarch: Separate the hardware flags into MMU index and PLVRui Wang
2022-11-04target/loongarch: Adjust the layout of hardware flags bit fieldsRui Wang
2022-07-04target/loongarch: Adjust functions and structure to support user-modeSong Gao
2022-06-06target/loongarch: Add other core instructions supportXiaojuan Yang
2022-06-06target/loongarch: Add TLB instruction supportXiaojuan Yang
2022-06-06target/loongarch: Add LoongArch IOCSR instructionXiaojuan Yang
2022-06-06target/loongarch: Add LoongArch CSR instructionXiaojuan Yang
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