| Age | Commit message (Expand) | Author |
|---|
| 2023-10-04 | target/i386: fix memory operand size for CVTPS2PD | Paolo Bonzini |
| 2023-10-04 | target/i386: generalize operand size "ph" for use in CVTPS2PD | Paolo Bonzini |
| 2023-10-04 | target/i386: Fix exception classes for MOVNTPS/MOVNTPD. | Ricky Zhou |
| 2023-10-04 | target/i386: Fix exception classes for SSE/AVX instructions. | Ricky Zhou |
| 2023-10-04 | target/i386: Fix and add some comments next to SSE/AVX instructions. | Ricky Zhou |
| 2023-10-04 | target/i386: fix operand size of unary SSE operations | Paolo Bonzini |
| 2023-09-11 | kvm: Introduce kvm_arch_get_default_type hook | Akihiko Odaki |
| 2023-08-05 | target/i386: Check CR0.TS before enter_mmx | Matt Borgerson |
| 2023-05-18 | target/i386: fix avx2 instructions vzeroall and vpermdq | Xinyu Li |
| 2023-05-18 | target/i386: fix operand size for VCOMI/VUCOMI instructions | Paolo Bonzini |
| 2023-04-27 | target/i386: Change wrong XFRM value in SGX CPUID leaf | Yang Zhong |
| 2023-03-29 | target/i386: Fix BZHI instruction | Richard Henderson |
| 2023-03-29 | target/i386: fix ADOX followed by ADCX | Paolo Bonzini |
| 2023-03-29 | target/i386: Fix C flag for BLSI, BLSMSK, BLSR | Richard Henderson |
| 2023-03-29 | target/i386: Fix BEXTR instruction | Richard Henderson |
| 2022-12-01 | target/i386: Always completely initialize TranslateFault | Richard Henderson |
| 2022-12-01 | target/i386: allow MMX instructions with CR4.OSFXSR=0 | Paolo Bonzini |
| 2022-11-15 | target/i386: hardcode R_EAX as destination register for LAHF/SAHF | Paolo Bonzini |
| 2022-11-15 | target/i386: fix cmpxchg with 32-bit register destination | Paolo Bonzini |
| 2022-11-03 | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging | Stefan Hajnoczi |
| 2022-11-02 | target/i386: Fix test for paging enabled | Richard Henderson |
| 2022-11-01 | target/i386: Expand eflags updates inline | Richard Henderson |
| 2022-11-01 | accel/tcg: Remove will_exit argument from cpu_restore_state | Richard Henderson |
| 2022-11-01 | target/i386: Use cpu_unwind_state_data for tpr access | Richard Henderson |
| 2022-10-31 | target/i386: Set maximum APIC ID to KVM prior to vCPU creation | Zeng Guang |
| 2022-10-31 | target/i386: Fix calculation of LOCK NEG eflags | Qi Hu |
| 2022-10-26 | Merge tag 'pull-tcg-20221026' of https://gitlab.com/rth7680/qemu into staging | Stefan Hajnoczi |
| 2022-10-26 | target/i386: Convert to tcg_ops restore_state_to_opc | Richard Henderson |
| 2022-10-25 | Merge tag 'trivial-branch-for-7.2-pull-request' of https://gitlab.com/laurent... | Stefan Hajnoczi |
| 2022-10-22 | Drop useless casts from g_malloc() & friends to pointer | Markus Armbruster |
| 2022-10-22 | target/i386: implement FMA instructions | Paolo Bonzini |
| 2022-10-20 | target/i386: implement F16C instructions | Paolo Bonzini |
| 2022-10-20 | target/i386: introduce function to set rounding mode from FPCW or MXCSR bits | Paolo Bonzini |
| 2022-10-20 | target/i386: decode-new: avoid out-of-bounds access to xmm_regs[-1] | Paolo Bonzini |
| 2022-10-18 | target/i386: remove old SSE decoder | Paolo Bonzini |
| 2022-10-18 | target/i386: move 3DNow to the new decoder | Paolo Bonzini |
| 2022-10-18 | target/i386: Enable AVX cpuid bits when using TCG | Paul Brook |
| 2022-10-18 | target/i386: implement VLDMXCSR/VSTMXCSR | Paolo Bonzini |
| 2022-10-18 | target/i386: implement XSAVE and XRSTOR of AVX registers | Paolo Bonzini |
| 2022-10-18 | target/i386: reimplement 0x0f 0x28-0x2f, add AVX | Paolo Bonzini |
| 2022-10-18 | target/i386: reimplement 0x0f 0x10-0x17, add AVX | Paolo Bonzini |
| 2022-10-18 | target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, add AVX | Paolo Bonzini |
| 2022-10-18 | target/i386: reimplement 0x0f 0x38, add AVX | Paolo Bonzini |
| 2022-10-18 | target/i386: Use tcg gvec ops for pmovmskb | Richard Henderson |
| 2022-10-18 | target/i386: reimplement 0x0f 0x3a, add AVX | Paolo Bonzini |
| 2022-10-18 | target/i386: clarify (un)signedness of immediates from 0F3Ah opcodes | Paolo Bonzini |
| 2022-10-18 | target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, add AVX | Paolo Bonzini |
| 2022-10-18 | target/i386: reimplement 0x0f 0x70-0x77, add AVX | Paolo Bonzini |
| 2022-10-18 | target/i386: reimplement 0x0f 0x78-0x7f, add AVX | Paolo Bonzini |
| 2022-10-18 | target/i386: reimplement 0x0f 0x50-0x5f, add AVX | Paolo Bonzini |
