Age | Commit message (Expand) | Author |
2020-12-16 | i386: move TCG accel files into tcg/ | Claudio Fontana |
2020-12-10 | target/i386: fix operand order for PDEP and PEXT | Paolo Bonzini |
2020-11-15 | x86 tcg cpus: Fix Lesser GPL version number | Chetan Pant |
2020-07-24 | target/i386: Save cc_op before loop insns | Richard Henderson |
2020-07-10 | target/i386: implement undocumented "smsw r32" behavior | Paolo Bonzini |
2020-07-10 | target/i386: remove gen_io_end | Paolo Bonzini |
2020-07-10 | target/i386: fix IEEE SSE floating-point exception raising | Joseph Myers |
2020-03-26 | linux-user/i386: Emulate x86_64 vsyscalls | Richard Henderson |
2020-01-15 | tcg: Search includes from the project root source directory | Philippe Mathieu-Daudé |
2019-12-18 | qemu_log_lock/unlock now preserves the qemu_logfile handle. | Robert Foley |
2019-10-28 | target/i386: fetch code with translator_ld | Emilio G. Cota |
2019-09-03 | tcg: TCGMemOp is now accelerator independent MemOp | Tony Nguyen |
2019-08-20 | icount: remove unnecessary gen_io_end calls | Pavel Dovgalyuk |
2019-05-22 | target/i386: Implement CPUID_EXT_RDRAND | Richard Henderson |
2019-04-24 | tcg: Hoist max_insns computation to tb_gen_code | Richard Henderson |
2019-04-09 | target/i386: Generate #UD for LOCK on a register increment | Peter Maydell |
2019-01-11 | avoid TABs in files that only contain a few | Paolo Bonzini |
2018-11-27 | target/i386: Generate #UD when applying LOCK to a register destination | Richard Henderson |
2018-10-30 | target/i386: Remove #ifdeffed-out icebp debugging hack | Peter Maydell |
2018-10-02 | target/i386: fix translation for icount mode | Pavel Dovgalyuk |
2018-10-02 | target/i386: rename HF_SVMI_MASK to HF_GUEST_MASK | Paolo Bonzini |
2018-10-02 | target/i386: move x86_64_hregs to DisasContext | Emilio G. Cota |
2018-10-02 | target/i386: move cpu_tmp1_i64 to DisasContext | Emilio G. Cota |
2018-10-02 | target/i386: move cpu_tmp3_i32 to DisasContext | Emilio G. Cota |
2018-10-02 | target/i386: move cpu_tmp2_i32 to DisasContext | Emilio G. Cota |
2018-10-02 | target/i386: move cpu_ptr1 to DisasContext | Emilio G. Cota |
2018-10-02 | target/i386: move cpu_ptr0 to DisasContext | Emilio G. Cota |
2018-10-02 | target/i386: move cpu_tmp4 to DisasContext | Emilio G. Cota |
2018-10-02 | target/i386: move cpu_tmp0 to DisasContext | Emilio G. Cota |
2018-10-02 | target/i386: move cpu_T1 to DisasContext | Emilio G. Cota |
2018-10-02 | target/i386: move cpu_T0 to DisasContext | Emilio G. Cota |
2018-10-02 | target/i386: move cpu_A0 to DisasContext | Emilio G. Cota |
2018-10-02 | target/i386: move cpu_cc_srcT to DisasContext | Emilio G. Cota |
2018-08-23 | fix "Missing break in switch" coverity reports | Paolo Bonzini |
2018-06-28 | target-i386: Allow interrupt injection after STGI | Jan Kiszka |
2018-06-28 | target/i386: Fix BLSR and BLSI | Richard Henderson |
2018-06-01 | tcg: Pass tb and index to tcg_gen_exit_tb separately | Richard Henderson |
2018-05-20 | tcg: fix s/compliment/complement/ typos | Emilio G. Cota |
2018-05-09 | translator: merge max_insns into DisasContextBase | Emilio G. Cota |
2018-04-09 | Add missing bit for SSE instr in VEX decoding | Eugene Minibaev |
2018-04-05 | target/i386: Fix andn instruction | Alexandro Sanchez Bach |
2017-12-29 | tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* | Richard Henderson |
2017-12-21 | target/i386: Fix handling of VEX prefixes | Peter Maydell |
2017-12-21 | target/i386: Fix compiler warnings | Stefan Weil |
2017-10-27 | Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into staging | Peter Maydell |
2017-10-25 | disas: Remove unused flags arguments | Richard Henderson |
2017-10-25 | target/i386: Convert to disas_set_info hook | Richard Henderson |
2017-10-24 | tcg: Initialize cpu_env generically | Richard Henderson |
2017-10-24 | tcg: define tcg_init_ctx and make tcg_ctx a pointer | Emilio G. Cota |
2017-10-24 | target/i386: check CF_PARALLEL instead of parallel_cpus | Emilio G. Cota |