Age | Commit message (Expand) | Author |
2023-12-12 | target/i386: Fix 32-bit wrapping of pc/eip computation | Richard Henderson |
2023-10-22 | target/i386: Use tcg_gen_ext_tl | Richard Henderson |
2023-10-22 | target/i386: Use i128 for 128 and 256-bit loads and stores | Richard Henderson |
2023-10-17 | target/i386: check intercept for XSETBV | Paolo Bonzini |
2023-10-07 | target/i386: Check for USER_ONLY definition instead of SOFTMMU one | Philippe Mathieu-Daudé |
2023-10-04 | accel/tcg: Replace CPUState.env_ptr with cpu_env() | Richard Henderson |
2023-10-03 | tcg: Rename cpu_env to tcg_env | Richard Henderson |
2023-09-26 | target/i386/translate: avoid shadowed local variables | Paolo Bonzini |
2023-09-20 | i386: spelling fixes | Michael Tokarev |
2023-09-01 | target/i386: raise FERR interrupt with iothread locked | Paolo Bonzini |
2023-06-29 | target/i386: emulate 64-bit ring 0 for linux-user if LM feature is set | Paolo Bonzini |
2023-06-26 | target/i386: implement SYSCALL/SYSRET in 32-bit emulators | Paolo Bonzini |
2023-06-26 | target/i386: implement RDPID in TCG | Paolo Bonzini |
2023-06-26 | target/i386: sysret and sysexit are privileged | Paolo Bonzini |
2023-06-26 | target/i386: AMD only supports SYSENTER/SYSEXIT in 32-bit mode | Paolo Bonzini |
2023-06-26 | target/i386: Intel only supports SYSCALL/SYSRET in long mode | Paolo Bonzini |
2023-06-26 | target/i386: TCG supports WBNOINVD | Paolo Bonzini |
2023-06-26 | target/i386: do not accept RDSEED if CPUID bit absent | Paolo Bonzini |
2023-06-26 | target/i386: fix INVD vmexit | Paolo Bonzini |
2023-06-20 | target/i386: Simplify i386_tr_init_disas_context() | Philippe Mathieu-Daudé |
2023-06-05 | accel/tcg: Introduce translator_io_start | Richard Henderson |
2023-06-05 | tcg: Pass TCGHelperInfo to tcg_gen_callN | Richard Henderson |
2023-04-23 | tcg: Replace tcg_abort with g_assert_not_reached | Richard Henderson |
2023-03-13 | target/i386: Avoid use of tcg_const_* throughout | Richard Henderson |
2023-03-05 | target/i386: Simplify POPF | Richard Henderson |
2023-03-05 | target/i386: Drop tcg_temp_free | Richard Henderson |
2023-03-01 | target/i386: Don't use tcg_temp_local_new | Richard Henderson |
2023-03-01 | accel/tcg: Pass max_insn to gen_intermediate_code by pointer | Richard Henderson |
2023-03-01 | target/i386: Replace `TARGET_TB_PCREL` with `CF_PCREL` | Anton Johansson |
2023-02-04 | target/i386: Inline cmpxchg16b | Richard Henderson |
2023-02-04 | target/i386: Inline cmpxchg8b | Richard Henderson |
2023-02-04 | target/i386: Split out gen_cmpxchg8b, gen_cmpxchg16b | Richard Henderson |
2022-11-15 | target/i386: hardcode R_EAX as destination register for LAHF/SAHF | Paolo Bonzini |
2022-11-15 | target/i386: fix cmpxchg with 32-bit register destination | Paolo Bonzini |
2022-11-03 | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging | Stefan Hajnoczi |
2022-11-01 | target/i386: Expand eflags updates inline | Richard Henderson |
2022-10-31 | target/i386: Fix calculation of LOCK NEG eflags | Qi Hu |
2022-10-26 | target/i386: Convert to tcg_ops restore_state_to_opc | Richard Henderson |
2022-10-22 | target/i386: implement FMA instructions | Paolo Bonzini |
2022-10-18 | target/i386: remove old SSE decoder | Paolo Bonzini |
2022-10-18 | target/i386: move 3DNow to the new decoder | Paolo Bonzini |
2022-10-18 | target/i386: reimplement 0x0f 0x28-0x2f, add AVX | Paolo Bonzini |
2022-10-18 | target/i386: reimplement 0x0f 0x10-0x17, add AVX | Paolo Bonzini |
2022-10-18 | target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, add AVX | Paolo Bonzini |
2022-10-18 | target/i386: reimplement 0x0f 0x38, add AVX | Paolo Bonzini |
2022-10-18 | target/i386: reimplement 0x0f 0x3a, add AVX | Paolo Bonzini |
2022-10-18 | target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, add AVX | Paolo Bonzini |
2022-10-18 | target/i386: reimplement 0x0f 0x70-0x77, add AVX | Paolo Bonzini |
2022-10-18 | target/i386: reimplement 0x0f 0x78-0x7f, add AVX | Paolo Bonzini |
2022-10-18 | target/i386: reimplement 0x0f 0x50-0x5f, add AVX | Paolo Bonzini |