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path: root/target/i386/cpu.c
AgeCommit message (Expand)Author
2024-07-31target/i386/cpu: Mask off SGX/SGX_LC feature words for non-PC machineZhao Liu
2024-07-31target/i386/cpu: Add dependencies of CPUID 0x12 leavesZhao Liu
2024-07-31target/i386/cpu: Explicitly express SGX_LC and SGX feature words dependencyZhao Liu
2024-07-31target/i386/cpu: Remove unnecessary SGX feature words checksZhao Liu
2024-07-31target/i386: Change unavail from u32 to u64Xiong Zhang
2024-07-16target/i386/tcg: Introduce x86_mmu_index_{kernel_,}plRichard Henderson
2024-07-03target/i386: add avx-vnni-int16 featurePaolo Bonzini
2024-07-03target/i386: do not include undefined bits in the AMD topoext leafPaolo Bonzini
2024-07-03target/i386: drop AMD machine check bits from Intel CPUIDPaolo Bonzini
2024-07-03target/i386: pass X86CPU to x86_cpu_get_supported_feature_wordPaolo Bonzini
2024-06-19target/i386: Remove X86CPU::kvm_no_smi_migration fieldPhilippe Mathieu-Daudé
2024-06-11i386/cpu: fixup number of addressable IDs for processor cores in the physical...Chuang Xu
2024-06-08i386: Add support for overflow recoveryJohn Allen
2024-06-08i386: Add support for SUCCOR featureJohn Allen
2024-06-08target/i386: enumerate VMX nested-exception supportXin Li
2024-06-08target/i386: add support for FRED in CPUID enumerationXin Li
2024-06-05i386/cpu: Set SEV-SNP CPUID bit when SNP enabledMichael Roth
2024-05-22i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 2...Zhao Liu
2024-05-22i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[4]Zhao Liu
2024-05-22i386: Add cache topology info in CPUCacheInfoZhao Liu
2024-05-22i386/cpu: Introduce module-id to X86CPUZhao Liu
2024-05-22i386: Expose module level in CPUID[0x1F]Zhao Liu
2024-05-22i386: Support modules_per_die in X86CPUTopoInfoZhao Liu
2024-05-22i386: Introduce module level cpu topology to CPUX86StateZhao Liu
2024-05-22i386/cpu: Decouple CPUID[0x1F] subleaf with specific topology levelZhao Liu
2024-05-22i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB]Zhao Liu
2024-05-22i386/cpu: Introduce bitmap to cache available CPU topology levelsZhao Liu
2024-05-22i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid()Zhao Liu
2024-05-22i386/cpu: Use APIC ID info get NumSharingCache for CPUID[0x8000001D].EAX[bits...Zhao Liu
2024-05-22i386/cpu: Use APIC ID info to encode cache topo in CPUID[4]Zhao Liu
2024-05-22i386/cpu: Fix i/d-cache topology to core level for Intel CPUZhao Liu
2024-05-22target/i386: add support for LAM in CPUID enumerationRobert Hoo
2024-05-10target/i386: fix feature dependency for WAITPKGPaolo Bonzini
2024-05-10target/i386: remove PCOMMIT from TCG, deprecate propertyPaolo Bonzini
2024-05-07target/i386: Fix CPUID encoding of Fn8000001E_ECXBabu Moger
2024-05-06Merge tag 'accel-20240506' of https://github.com/philmd/qemu into stagingRichard Henderson
2024-05-06accel/tcg: Access tcg_cflags with getter / setterPhilippe Mathieu-Daudé
2024-05-03target/i386: Introduce SapphireRapids-v3 to add missing featuresLei Wang
2024-04-29target/i386/cpu: Remove "x86" prefix from the CPU listThomas Huth
2024-04-25hw, target: Add ResetType argument to hold and exit phase methodsPeter Maydell
2024-04-23target/i386/cpu: Merge the warning and error messages for AMD HT checkZhao Liu
2024-04-23target/i386/cpu: Consolidate the use of warn_report_once()Zhao Liu
2024-04-23target/i386: Export RFDS bit to guestsPawan Gupta
2024-04-23target/i386: Add new CPU model SierraForestTao Su
2024-04-23target/i386: Introduce Icelake-Server-v7 to enable TSXZhenzhong Duan
2024-04-18target/i386: add guest-phys-bits cpu propertyGerd Hoffmann
2024-03-18target/i386: fix direction of "32-bit MMU" testPaolo Bonzini
2024-03-12target: Replace CPU_GET_CLASS(cpu -> obj) in cpu_reset_hold() handlerPhilippe Mathieu-Daudé
2024-02-28Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell
2024-02-28gdbstub: Infer number of core registers from XMLAkihiko Odaki
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