Age | Commit message (Expand) | Author |
2023-06-20 | meson: Replace softmmu_ss -> system_ss | Philippe Mathieu-Daudé |
2023-06-19 | target/arm: Convert load/store tags insns to decodetree | Peter Maydell |
2023-06-19 | target/arm: Convert load/store single structure to decodetree | Peter Maydell |
2023-06-19 | target/arm: Convert load/store (multiple structures) to decodetree | Peter Maydell |
2023-06-19 | target/arm: Convert LDAPR/STLR (imm) to decodetree | Peter Maydell |
2023-06-19 | target/arm: Convert load (pointer auth) insns to decodetree | Peter Maydell |
2023-06-19 | target/arm: Convert atomic memory ops to decodetree | Peter Maydell |
2023-06-19 | target/arm: Convert LDR/STR reg+reg to decodetree | Peter Maydell |
2023-06-19 | target/arm: Convert LDR/STR with 12-bit immediate to decodetree | Peter Maydell |
2023-06-19 | target/arm: Convert ld/st reg+imm9 insns to decodetree | Peter Maydell |
2023-06-19 | target/arm: Convert load/store-pair to decodetree | Peter Maydell |
2023-06-19 | target/arm: Convert load reg (literal) group to decodetree | Peter Maydell |
2023-06-19 | target/arm: Convert LDXP, STXP, CASP, CAS to decodetree | Peter Maydell |
2023-06-19 | target/arm: Convert load/store exclusive and ordered to decodetree | Peter Maydell |
2023-06-19 | target/arm: Convert exception generation instructions to decodetree | Peter Maydell |
2023-06-19 | target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree | Peter Maydell |
2023-06-19 | target/arm: Convert MSR (immediate) to decodetree | Peter Maydell |
2023-06-19 | target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree | Peter Maydell |
2023-06-19 | target/arm: Convert barrier insns to decodetree | Peter Maydell |
2023-06-19 | target/arm: Convert hint instruction space to decodetree | Peter Maydell |
2023-06-19 | target/arm: Consistently use finalize_memop_asimd() for ASIMD loads/stores | Peter Maydell |
2023-06-19 | target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decode | Peter Maydell |
2023-06-19 | target/arm: Return correct result for LDG when ATA=0 | Peter Maydell |
2023-06-19 | target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics | Peter Maydell |
2023-06-15 | target/arm: Allow users to set the number of VFP registers | Cédric Le Goater |
2023-06-07 | target/arm: Only include tcg/oversized-guest.h if CONFIG_TCG | Richard Henderson |
2023-06-06 | Merge tag 'pull-target-arm-20230606' of https://git.linaro.org/people/pmaydel... | Richard Henderson |
2023-06-06 | target/arm: trap DCC access in user mode emulation | Zhuojia Shen |
2023-06-06 | target/arm: allow DC CVA[D]P in user mode emulation | Zhuojia Shen |
2023-06-06 | target/arm: Enable FEAT_LSE2 for -cpu max | Richard Henderson |
2023-06-06 | target/arm: Move mte check for store-exclusive | Richard Henderson |
2023-06-06 | target/arm: Relax ordered/atomic alignment checks for LSE2 | Richard Henderson |
2023-06-06 | target/arm: Add SCTLR.nAA to TBFLAG_A64 | Richard Henderson |
2023-06-06 | target/arm: Check alignment in helper_mte_check | Richard Henderson |
2023-06-06 | target/arm: Pass single_memop to gen_mte_checkN | Richard Henderson |
2023-06-06 | target/arm: Pass memop to gen_mte_check1* | Richard Henderson |
2023-06-06 | target/arm: Hoist finalize_memop out of do_fp_{ld, st} | Richard Henderson |
2023-06-06 | target/arm: Hoist finalize_memop out of do_gpr_{ld, st} | Richard Henderson |
2023-06-06 | target/arm: Load/store integer pair with one tcg operation | Richard Henderson |
2023-06-06 | target/arm: Sink gen_mte_check1 into load/store_exclusive | Richard Henderson |
2023-06-06 | target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r | Richard Henderson |
2023-06-06 | target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G | Richard Henderson |
2023-06-06 | target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld} | Richard Henderson |
2023-06-06 | target/arm: Use tcg_gen_qemu_ld_i128 for LDXP | Richard Henderson |
2023-06-06 | target/arm: Introduce finalize_memop_{atom,pair} | Richard Henderson |
2023-06-06 | target/arm: Add feature test for FEAT_LSE2 | Richard Henderson |
2023-06-06 | target/arm: Add commentary for CPUARMState.exclusive_high | Richard Henderson |
2023-06-06 | hvf: add guest debugging handlers for Apple Silicon hosts | Francesco Cagnin |
2023-06-06 | hvf: add breakpoint handlers | Francesco Cagnin |
2023-06-06 | hvf: handle access for more registers | Francesco Cagnin |