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QEMU is a generic and open source machine & userspace emulator and virtualizer
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translate-a64.c
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Author
2021-07-21
accel/tcg: Remove TranslatorOps.breakpoint_check
Richard Henderson
2021-07-09
target/arm: Use translator_use_goto_tb for aarch64
Richard Henderson
2021-07-09
tcg: Avoid including 'trace-tcg.h' in target translate.c
Philippe Mathieu-Daudé
2021-07-02
target/arm: Use dup_const() instead of bitfield_replicate()
Peter Maydell
2021-07-02
target/arm: Use asimd_imm_const for A64 decode
Peter Maydell
2021-06-29
target/arm: Improve vector REV
Richard Henderson
2021-06-29
target/arm: Improve REV32
Richard Henderson
2021-06-29
tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64
Richard Henderson
2021-06-15
target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16
Richard Henderson
2021-06-15
target/arm: Remove fprintf from disas_simd_mod_imm
Richard Henderson
2021-06-15
target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16
Richard Henderson
2021-06-03
target/arm: Implement bfloat widening fma (indexed)
Richard Henderson
2021-06-03
target/arm: Implement bfloat widening fma (vector)
Richard Henderson
2021-06-03
target/arm: Implement bfloat16 matrix multiply accumulate
Richard Henderson
2021-06-03
target/arm: Implement bfloat16 dot product (indexed)
Richard Henderson
2021-06-03
target/arm: Implement bfloat16 dot product (vector)
Richard Henderson
2021-06-03
target/arm: Implement vector float32 to bfloat16 conversion
Richard Henderson
2021-06-03
target/arm: Implement scalar float32 to bfloat16 conversion
Richard Henderson
2021-06-03
target/arm: Unify unallocated path in disas_fp_1src
Richard Henderson
2021-06-03
target/arm: Mark LDS{MIN,MAX} as signed operations
Richard Henderson
2021-05-25
target/arm: Implement integer matrix multiply accumulate
Richard Henderson
2021-05-25
target/arm: Implement aarch64 SUDOT, USDOT
Richard Henderson
2021-05-25
target/arm: Pass separate addend to FCMLA helpers
Richard Henderson
2021-05-25
target/arm: Pass separate addend to {U, S}DOT helpers
Richard Henderson
2021-05-25
target/arm: Implement SVE2 XAR
Richard Henderson
2021-05-10
target/arm: Share unallocated_encoding() and gen_exception_insn()
Peter Maydell
2021-04-30
target/arm: Enforce alignment for aa64 vector LDn/STn (single)
Richard Henderson
2021-04-30
target/arm: Enforce alignment for aa64 vector LDn/STn (multiple)
Richard Henderson
2021-04-30
target/arm: Use MemOp for size + endian in aa64 vector ld/st
Richard Henderson
2021-04-30
target/arm: Enforce alignment for aa64 load-acq/store-rel
Richard Henderson
2021-04-30
target/arm: Use finalize_memop for aa64 fpr load/store
Richard Henderson
2021-04-30
target/arm: Use finalize_memop for aa64 gpr load/store
Richard Henderson
2021-04-30
target/arm: Add ALIGN_MEM to TBFLAG_ANY
Richard Henderson
2021-04-30
target/arm: Introduce CPUARMTBFlags
Richard Henderson
2021-04-30
target/arm: Add wrapper macros for accessing tbflags
Richard Henderson
2021-04-30
target/arm: Rename TBFLAG_ANY, PSTATE_SS
Richard Henderson
2021-04-30
target/arm: Remove log2_esize parameter to gen_mte_checkN
Richard Henderson
2021-04-30
target/arm: Merge mte_check1, mte_checkN
Richard Henderson
2021-04-30
target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1
Richard Henderson
2021-03-10
semihosting: Move include/hw/semihosting/ -> include/semihosting/
Philippe Mathieu-Daudé
2021-03-05
target/arm: Speed up aarch64 TBL/TBX
Richard Henderson
2021-03-05
target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe
Rebecca Cran
2021-02-16
target/arm: Improve gen_top_byte_ignore
Richard Henderson
2021-02-11
target/arm: Add support for FEAT_DIT, Data Independent Timing
Rebecca Cran
2021-01-19
target/arm: add MMU stage 1 for Secure EL2
Rémi Denis-Courmont
2021-01-07
tcg: Make DisasContextBase.tb const
Richard Henderson
2020-11-15
arm tcg cpus: Fix Lesser GPL version number
Chetan Pant
2020-11-10
target/arm: Don't use '#' flag of printf format
Xinhao Zhang
2020-10-27
linux-user: Set PAGE_TARGET_1 for TARGET_PROT_BTI
Richard Henderson
2020-09-01
target/arm/translate-a64:Remove redundant statement in disas_simd_two_reg_mis...
Chen Qun
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