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path: root/target-xtensa/translate.c
AgeCommit message (Expand)Author
2014-06-05softmmu: introduce cpu_ldst.hPaolo Bonzini
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson
2014-05-26target-xtensa: fix cross-page jumps/calls at the end of TBMax Filippov
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber
2014-02-24target-xtensa: provide HW confg ID registersMax Filippov
2014-02-24target-xtensa: add basic checks to icache opcodesMax Filippov
2014-02-24target-xtensa: add basic checks to dcache opcodesMax Filippov
2014-02-24target-xtensa: add RRRI4 opcode format fieldsMax Filippov
2013-10-15target-xtensa: add in_asm loggingMax Filippov
2013-10-10tcg: Move helper registration into tcg_context_initRichard Henderson
2013-09-02tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson
2013-07-29target-xtensa: check register window inlineMax Filippov
2013-07-29target-xtensa: don't generate dead code to access invalid SRsMax Filippov
2013-07-29target-xtensa: avoid double-stopping at breakpointsMax Filippov
2013-07-23cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber
2013-07-09target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPUAndreas Färber
2013-07-09target-xtensa: gen_intermediate_code_internal() should be inlinedAndreas Färber
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber
2013-03-03gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell
2013-02-23target-xtensa: Use add2/sub2 for macRichard Henderson
2013-02-23target-xtensa: Use mul*2 for mul*hiRichard Henderson
2012-12-22target-xtensa: fix search_pc for the last TB opcodeMax Filippov
2012-12-19softmmu: move include files to include/sysemu/Paolo Bonzini
2012-12-19misc: move include files to include/qemu/Paolo Bonzini
2012-12-19exec: move include files to include/exec/Paolo Bonzini
2012-12-19build: kill libdis, move disassemblers to disas/Paolo Bonzini
2012-12-08target-xtensa: use movcond where possibleMax Filippov
2012-12-08target-xtensa: implement MISC SRMax Filippov
2012-12-08target-xtensa: better control rsr/wsr/xsr access to SRsMax Filippov
2012-12-08target-xtensa: restrict available SRs by enabled optionsMax Filippov
2012-12-08target-xtensa: implement CACHEATTR SRMax Filippov
2012-12-08target-xtensa: implement ATOMCTL SRMax Filippov
2012-12-08TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin
2012-12-08TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin
2012-12-08TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin
2012-11-17TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin
2012-11-17TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin
2012-11-10target-xtensa: avoid using cpu_single_envBlue Swirl
2012-10-06target-xtensa: de-optimize EXTUIAurelien Jarno
2012-09-27Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson
2012-09-22target-xtensa: implement coprocessor context optionMax Filippov
2012-09-22target-xtensa: implement FP1 groupMax Filippov
2012-09-22target-xtensa: implement FP0 conversionsMax Filippov
2012-09-22target-xtensa: implement FP0 arithmeticMax Filippov
2012-09-22target-xtensa: implement LSCX and LSCI groupsMax Filippov
2012-09-22target-xtensa: add FP registersMax Filippov
2012-09-21target-xtensa: don't emit extra tcg_gen_goto_tbMax Filippov
2012-09-21target-xtensa: fix extui shift amountMax Filippov
2012-07-28target-xtensa: fix big-endian BBS/BBC implementationMax Filippov
2012-06-10target-xtensa: switch to AREG0-free modeMax Filippov
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