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QEMU is a generic and open source machine & userspace emulator and virtualizer
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target-tricore
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translate.c
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Author
2016-03-23
target-tricore: Add ftoi and itof instructions
Bastian Koppelmann
2016-03-23
target-tricore: Add cmp.f instruction
Bastian Koppelmann
2016-03-23
target-tricore: Add div.f instruction
Bastian Koppelmann
2016-03-23
target-tricore: Add mul.f instruction
Bastian Koppelmann
2016-03-23
target-tricore: add add.f/sub.f instructions
Bastian Koppelmann
2016-03-23
target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide
Bastian Koppelmann
2016-03-23
target-tricore: Add FPU infrastructure
Bastian Koppelmann
2016-03-23
target-tricore: add missing break in insn decode switch stmt
Bastian Koppelmann
2016-03-01
tcg: Add type for vCPU pointers
LluĂs Vilanova
2016-02-25
target-tricore: add opd trap generation
Bastian Koppelmann
2016-02-25
target-tricore: add illegal opcode trap generation
Bastian Koppelmann
2016-02-25
target-tricore: Add trap handling & SOVF/OVF traps
Bastian Koppelmann
2016-02-09
tcg: Change tcg_global_mem_new_* to take a TCGv_ptr
Richard Henderson
2016-02-03
log: do not unnecessarily include qom/cpu.h
Paolo Bonzini
2016-01-29
tricore: Clean up includes
Peter Maydell
2015-10-07
tcg: Remove gen_intermediate_code_pc
Richard Henderson
2015-10-07
tcg: Pass data argument to restore_state_to_opc
Richard Henderson
2015-10-07
tcg: Add TCG_MAX_INSNS
Richard Henderson
2015-10-07
target-*: Increment num_insns immediately after tcg_gen_insn_start
Richard Henderson
2015-10-07
target-*: Unconditionally emit tcg_gen_insn_start
Richard Henderson
2015-09-11
tlb: Add "ifetch" argument to cpu_mmu_index()
Benjamin Herrenschmidt
2015-08-24
tcg: Remove tcg_gen_trunc_i64_i32
Richard Henderson
2015-08-24
tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32
Richard Henderson
2015-06-22
disas: Remove uses of CPU env
Peter Crosthwaite
2015-05-30
target-tricore: fix BOL_ST_H_LONGOFF using ld
Bastian Koppelmann
2015-05-30
target-tricore: fix msub32_q producing the wrong overflow bit
Bastian Koppelmann
2015-05-30
target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the result
Bastian Koppelmann
2015-05-22
target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA
Bastian Koppelmann
2015-05-22
target-tricore: add FRET instructions of the v1.6 ISA
Bastian Koppelmann
2015-05-22
target-tricore: add FCALL instructions of the v1.6 ISA
Bastian Koppelmann
2015-05-22
target-tricore: add SYS_RESTORE instruction of the v1.6 ISA
Bastian Koppelmann
2015-05-22
target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA
Bastian Koppelmann
2015-05-22
target-tricore: add SWAPMSK instructions of the v1.6.1 ISA
Bastian Koppelmann
2015-05-22
target-tricore: add CMPSWP instructions of the v1.6.1 ISA
Bastian Koppelmann
2015-05-22
target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA
Bastian Koppelmann
2015-05-11
target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory ...
Bastian Koppelmann
2015-05-11
target-tricore: Fix LOOP using wrong register for compare
Bastian Koppelmann
2015-03-30
target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..
Bastian Koppelmann
2015-03-24
target-tricore: fix RRPW_DEXTR using wrong reg
Bastian Koppelmann
2015-03-24
target-tricore: fix DVINIT_HU/BU calculating overflow before result
Bastian Koppelmann
2015-03-19
Fix typos in comments
Viswesh
2015-03-16
target-tricore: Add instructions of SYS opcode format
Bastian Koppelmann
2015-03-16
target-tricore: Add instructions of RRRW opcode format
Bastian Koppelmann
2015-03-16
target-tricore: Add instructions of RRRR opcode format
Bastian Koppelmann
2015-03-16
target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as fi...
Bastian Koppelmann
2015-03-16
target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as fi...
Bastian Koppelmann
2015-03-16
target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as fi...
Bastian Koppelmann
2015-03-13
tcg: Change translator-side labels to a pointer
Richard Henderson
2015-03-03
target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as fi...
Bastian Koppelmann
2015-03-03
target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as fi...
Bastian Koppelmann
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