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path: root/target-ppc/translate.c
AgeCommit message (Expand)Author
2015-12-17ppc: cleanup loggingPaolo Bonzini
2015-12-17qemu-log: introduce qemu_log_separatePaolo Bonzini
2015-11-12PPC: Allow Rc bit to be set on mtsprAlexander Graf
2015-10-28target-*: Advance pc after recognizing a breakpointRichard Henderson
2015-10-23ppc: Add mmu_model defines for arch 2.03 and 2.07Benjamin Herrenschmidt
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson
2015-10-07target-*: Introduce and use cpu_breakpoint_testRichard Henderson
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson
2015-10-07tcg: Rename debug_insn_start to insn_startRichard Henderson
2015-09-20target-ppc: fix xscmpodp and xscmpudp decodingAurelien Jarno
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite
2015-03-13tcg: Change translator-side labels to a pointerRichard Henderson
2015-03-09display cpu id dump stateTristan Gingold
2015-02-12tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson
2015-02-12tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson
2015-01-10Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' int...Peter Maydell
2015-01-07target-ppc: Mark SR() and gen_sync_exception() as !CONFIG_USER_ONLYPeter Maydell
2015-01-07target-ppc: Introduce Privileged TM NoopsTom Musta
2015-01-07target-ppc: Introduce tcheckTom Musta
2015-01-07target-ppc: Introduce TM NoopsTom Musta
2015-01-07target-ppc: Introduce tbeginTom Musta
2015-01-07target-ppc: Introduce tm_enabled Bit to CPU StateTom Musta
2015-01-07target-ppc: Eliminate set_fprf Argument From helper_compute_fprfTom Musta
2015-01-07target-ppc: Eliminate set_fprf Argument From gen_compute_fprfTom Musta
2015-01-07target-ppc: Fully Migrate to gen_set_cr1_from_fpscrTom Musta
2015-01-07target-ppc: mffs. Should Set CR1 from FPSCR BitsTom Musta
2015-01-07target-ppc: Fix Floating Point Move Instructions That Set CR1Tom Musta
2015-01-07target-ppc: Load/Store Vector Element Storage AlignmentTom Musta
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini
2014-12-23target-ppc: pass DisasContext to SPR generator functionsPaolo Bonzini
2014-11-20target-ppc: Altivec's mtvscr Decodes Wrong RegisterTom Musta
2014-11-04target-ppc: Fix Altivec Round OpcodesTom Musta
2014-11-04ppc: do not look at the MMU index to detect PR/HV modePaolo Bonzini
2014-11-04target-ppc : Allow fc[tf]id[*] mnemonics for non TARGET_PPC64Pierre Mallard
2014-11-04ppc: compute mask from BI using right shiftPaolo Bonzini
2014-11-04ppc: rename gen_set_cr6_from_fpscrPaolo Bonzini
2014-09-08target-ppc: Implement mulldo with TCGTom Musta
2014-09-08target-ppc: Clean up mullwoTom Musta
2014-09-08target-ppc: Clean Up mullwTom Musta
2014-09-08target-ppc: Optimize rlwnm MB=0 ME=31Tom Musta
2014-09-08target-ppc: Optimize rlwinm MB=0 ME=31Tom Musta
2014-09-08target-ppc: Special Case of rlwimi Should Use DepositTom Musta
2014-09-08target-ppc: Bug Fix: srawiTom Musta
2014-09-08target-ppc: Bug Fix: mullwTom Musta
2014-09-08target-ppc: Bug Fix: mullwoTom Musta
2014-09-08target-ppc: Bug Fix: rlwimiTom Musta
2014-09-08target-ppc: Bug Fix: rlwnmTom Musta
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