Age | Commit message (Expand) | Author |
2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth |
2016-11-02 | x86: add AVX512_4VNNIW and AVX512_4FMAPS features | Luwei Kang |
2016-10-24 | pc: apic_common: Extend APIC ID property to 32bit | Igor Mammedov |
2016-10-07 | qemu-tech: document lazy condition code evaluation in cpu.h | Paolo Bonzini |
2016-09-27 | target-i386: Move xsave component mask to features array | Eduardo Habkost |
2016-09-27 | target-i386: xsave: Calculate set of xsave components on realize | Eduardo Habkost |
2016-09-27 | target-i386: Automatically set level/xlevel/xlevel2 when needed | Eduardo Habkost |
2016-09-27 | target-i386: Add a marker to end of the region zeroed on reset | Eduardo Habkost |
2016-09-19 | target-i386: Use struct X86XSaveArea in fpu_helper.c | Richard Henderson |
2016-09-14 | target-i386: fix ordering of fields in CPUX86State | Paolo Bonzini |
2016-09-09 | target-i386: present virtual L3 cache info for vcpus | Longpeng(Mike) |
2016-09-05 | target-i386: Add more Intel AVX-512 instructions support | Luwei Kang |
2016-07-20 | target-i386: Add support for UMIP and RDPID CPUID bits | Paolo Bonzini |
2016-07-20 | target-i386: Add socket/core/thread properties to X86CPU | Igor Mammedov |
2016-07-20 | target-i386: Set physical address bits based on host | Dr. David Alan Gilbert |
2016-07-20 | target-i386: Use uint32_t for X86CPU.apic_id | Igor Mammedov |
2016-07-20 | target-i386: Fill high bits of mtrr mask | Dr. David Alan Gilbert |
2016-07-20 | target-i386: Allow physical address bits to be set | Dr. David Alan Gilbert |
2016-07-20 | target-i386: Provide TCG_PHYS_ADDR_BITS | Dr. David Alan Gilbert |
2016-07-19 | target-i386: Remove redundant HF_SOFTMMU_MASK | Sergey Fedorov |
2016-07-12 | target-*: Clean up cpu.h header guards | Markus Armbruster |
2016-07-07 | target-i386: Publish advised value of MSR_IA32_FEATURE_CONTROL via fw_cfg | Haozhong Zhang |
2016-07-07 | target-i386: kvm: Add basic Intel LMCE support | Ashok Raj |
2016-07-07 | target-i386: Report hyperv feature words through qom | Evgeny Yakovlev |
2016-07-07 | pc: Parse CPU features only once | Igor Mammedov |
2016-06-29 | target-*: Don't redefine cpu_exec() | Peter Crosthwaite |
2016-06-14 | target-i386: Implement CPUID[0xB] (Extended Topology Enumeration) | Radim Krčmář |
2016-05-23 | target-i386: kvm: Allocate kvm_msrs struct once per VCPU | Eduardo Habkost |
2016-05-23 | cpu: Eliminate cpudef_init(), cpudef_setup() | Eduardo Habkost |
2016-05-23 | target-i386: Define structs for layout of xsave area | Eduardo Habkost |
2016-05-19 | cpu: move exec-all.h inclusion out of cpu.h | Paolo Bonzini |
2016-05-19 | apic: move target-dependent definitions to cpu.h | Paolo Bonzini |
2016-05-19 | target-i386: make cpu-qom.h not target specific | Paolo Bonzini |
2016-05-18 | Fix some typos found by codespell | Stefan Weil |
2016-05-12 | tb: consistently use uint32_t for tb->flags | Emilio G. Cota |
2016-03-24 | target-i386: implement PKE for TCG | Paolo Bonzini |
2016-02-25 | Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging | Peter Maydell |
2016-02-25 | target-i386: fix confusion in xcr0 bit position vs. mask | Paolo Bonzini |
2016-02-23 | all: Clean up includes | Peter Maydell |
2016-02-13 | target-i386: Enable control registers for MPX | Richard Henderson |
2016-01-21 | target-i386: Add PKU and and OSPKE support | Huaitong Han |
2016-01-21 | target-i386: Add support to migrate vcpu's TSC rate | Haozhong Zhang |
2016-01-21 | target-i386: Add suffixes to MMReg struct fields | Eduardo Habkost |
2016-01-21 | target-i386: Define MMREG_UNION macro | Eduardo Habkost |
2016-01-21 | target-i386: Define MMXReg._d field | Eduardo Habkost |
2016-01-21 | target-i386: Rename XMM_[BWLSDQ] helpers to ZMM_* | Eduardo Habkost |
2016-01-21 | target-i386: Rename struct XMMReg to ZMMReg | Eduardo Habkost |
2016-01-21 | target-i386: Use a _q array on MMXReg too | Eduardo Habkost |
2016-01-21 | target-i386: Rename optimize_flags_init() | Eduardo Habkost |
2015-12-17 | target-i386/kvm: Hyper-V SynIC timers MSR's support | Andrey Smetanin |