Age | Commit message (Expand) | Author |
2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth |
2016-10-26 | target-arm: remove EXCP_STREX + cpu_exclusive_{test, info} | Emilio G. Cota |
2016-10-17 | target-arm: Infrastucture changes to enable handling of tagged address loadin... | Thomas Hanson |
2016-06-06 | target-arm: A64: Create Instruction Syndromes for Data Aborts | Edgar E. Iglesias |
2016-03-04 | target-arm: introduce disas flag for endianness | Paolo Bonzini |
2016-03-04 | target-arm: implement SCTLR.B, drop bswap_code | Paolo Bonzini |
2016-03-01 | tcg: Add type for vCPU pointers | LluĂs Vilanova |
2015-10-07 | tcg: Remove gen_intermediate_code_pc | Richard Henderson |
2015-09-14 | target-arm: Introduce DisasCompare | Richard Henderson |
2015-09-14 | target-arm: Share all common TCG temporaries | Richard Henderson |
2015-09-08 | target-arm: Fix default_exception_el() function for the case when EL3 is not ... | Sergey Sorokin |
2015-07-06 | target-arm: Split DISAS_YIELD from DISAS_WFE | Peter Maydell |
2015-05-29 | target-arm: Extend FP checks to use an EL | Greg Bellows |
2015-05-29 | target-arm: Add exception target el infrastructure | Greg Bellows |
2015-03-13 | tcg: Change translator-side labels to a pointer | Richard Henderson |
2015-02-05 | target-arm: Define correct mmu_idx values and pass them in TB flags | Peter Maydell |
2014-12-11 | target-arm: add non-secure Translation Block flag | Sergey Fedorov |
2014-10-24 | target-arm: rename arm_current_pl to arm_current_el | Greg Bellows |
2014-10-24 | target-arm: Add support for A32 and T32 HVC and SMC insns | Peter Maydell |
2014-09-29 | target-arm: Don't handle c15_cpar changes via tb_flush() | Peter Maydell |
2014-08-19 | target-arm: Implement ARMv8 single-step handling for A64 code | Peter Maydell |
2014-05-27 | target-arm: Use a 1:1 mapping between EL and MMU index | Edgar E. Iglesias |
2014-05-27 | target-arm: Move get_mem_index to translate.h | Edgar E. Iglesias |
2014-04-17 | target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32 | Peter Maydell |
2014-04-17 | target-arm: A64: Add assertion that FP access was checked | Peter Maydell |
2014-04-17 | target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set | Peter Maydell |
2014-04-17 | target-arm: Add support for generating exceptions with syndrome information | Peter Maydell |
2014-03-17 | target-arm: A64: Implement PMULL instruction | Peter Maydell |
2014-03-10 | target-arm: Implement WFE as a yield operation | Peter Maydell |
2014-01-07 | target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder | Peter Maydell |
2013-12-17 | target-arm: A64: add support for conditional branches | Alexander Graf |
2013-12-17 | target-arm: A64: add support for B and BL insns | Alexander Graf |
2013-12-17 | target-arm: Split A64 from A32/T32 gen_intermediate_code_internal() | Peter Maydell |
2013-09-10 | target-arm: Add AArch64 translation stub | Alexander Graf |
2013-09-10 | target-arm: Prepare translation for AArch64 code | Alexander Graf |
2013-09-10 | target-arm: Export cpu_env | Alexander Graf |
2013-09-10 | target-arm: Extract the disas struct to a header file | Alexander Graf |