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path: root/target-arm/translate-a64.c
AgeCommit message (Expand)Author
2016-03-04target-arm: introduce tbflag for endiannessPeter Crosthwaite
2016-03-04target-arm: a64: Add endianness supportPeter Crosthwaite
2016-03-04target-arm: introduce disas flag for endiannessPaolo Bonzini
2016-03-04target-arm: implement SCTLR.B, drop bswap_codePaolo Bonzini
2016-02-11target-arm: Add isread parameter to CPAccessFnsPeter Maydell
2016-02-09tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson
2016-02-03log: do not unnecessarily include qom/cpu.hPaolo Bonzini
2016-01-18target-arm: Clean up includesPeter Maydell
2015-11-24target-arm/translate-a64.c: Correct unallocated checks for ldst_exclPeter Maydell
2015-11-12target-arm: Update PC before calling gen_helper_check_breakpoints()Sergey Fedorov
2015-11-03target-arm: Report S/NS status in the CPU debug logsPeter Maydell
2015-11-03target-arm: Bring AArch64 debug CPU display of PSTATE into line with AArch32Peter Maydell
2015-10-28target-*: Advance pc after recognizing a breakpointRichard Henderson
2015-10-16target-arm: Fix CPU breakpoint handlingSergey Fedorov
2015-10-16target-arm: Break the TB after ISB to execute self-modified code correctlySergey Sorokin
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson
2015-10-07target-arm: Add condexec state to insn_startRichard Henderson
2015-10-07target-*: Introduce and use cpu_breakpoint_testRichard Henderson
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson
2015-10-07tcg: Rename debug_insn_start to insn_startRichard Henderson
2015-09-14target-arm: Use tcg_gen_extrh_i64_i32Richard Henderson
2015-09-14target-arm: Recognize RORRichard Henderson
2015-09-14target-arm: Eliminate unnecessary zero-extend in disas_bitfieldRichard Henderson
2015-09-14target-arm: Recognize UXTB, UXTH, LSR, LSLRichard Henderson
2015-09-14target-arm: Recognize SXTB, SXTH, SXTW, ASRRichard Henderson
2015-09-14target-arm: Implement fcsel with movcondRichard Henderson
2015-09-14target-arm: Implement ccmp branchlessRichard Henderson
2015-09-14target-arm: Use setcond and movcond for cselRichard Henderson
2015-09-14target-arm: Share all common TCG temporariesRichard Henderson
2015-09-08target-arm: Fix default_exception_el() function for the case when EL3 is not ...Sergey Sorokin
2015-09-07target-arm: Wire up HLT 0xf000 as the A64 semihosting instructionPeter Maydell
2015-08-24tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson
2015-07-06target-arm: Split DISAS_YIELD from DISAS_WFEPeter Maydell
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite
2015-05-29target-arm: Don't halt on WFI unless we don't have any workPeter Maydell
2015-05-29target-arm: Extend FP checks to use an ELGreg Bellows
2015-05-29target-arm: Make singlestate TB flags common between AArch32/64Peter Maydell
2015-05-29target-arm: Add exception target el infrastructureGreg Bellows
2015-03-13tcg: Change translator-side labels to a pointerRichard Henderson
2015-02-13Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150212' into stagingPeter Maydell
2015-02-13target-arm: A64: Avoid signed shifts in disas_ldst_pair()Peter Maydell
2015-02-13target-arm: A64: Avoid left shifting negative integers in disas_pc_rel_addrPeter Maydell
2015-02-13target-arm: A64: Fix handling of rotate in logic_imm_decode_wmaskPeter Maydell
2015-02-13target-arm: A64: Fix shifts into sign bitPeter Maydell
2015-02-12tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson
2015-02-12tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson
2015-02-05target-arm: Use correct mmu_idx for unprivileged loads and storesPeter Maydell
2015-02-05target-arm: Define correct mmu_idx values and pass them in TB flagsPeter Maydell
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