Age | Commit message (Expand) | Author |
2015-04-01 | target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc) | Peter Maydell |
2015-02-13 | target-arm: Add 32/64-bit register sync | Greg Bellows |
2015-02-05 | target-arm: Squash input denormals in FRECPS and FRSQRTS | Peter Maydell |
2015-02-05 | Fix FMULX not squashing denormalized inputs when FZ is set. | Xiangyu Hu |
2014-10-24 | target-arm: rename arm_current_pl to arm_current_el | Greg Bellows |
2014-10-24 | target-arm: add emulation of PSCI calls for system emulation | Rob Herring |
2014-10-24 | target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes | Rob Herring |
2014-09-29 | target-arm: Add support for VIRQ and VFIQ | Edgar E. Iglesias |
2014-09-29 | target-arm: A64: Emulate the SMC insn | Edgar E. Iglesias |
2014-09-29 | target-arm: Add a Hypervisor Trap exception type | Edgar E. Iglesias |
2014-09-29 | target-arm: A64: Emulate the HVC insn | Edgar E. Iglesias |
2014-09-29 | target-arm: A64: Correct updates to FAR and ESR on exceptions | Edgar E. Iglesias |
2014-09-29 | target-arm: A64: Refactor aarch64_cpu_do_interrupt | Edgar E. Iglesias |
2014-08-04 | target-arm: Make far_el1 an array | Edgar E. Iglesias |
2014-08-04 | target-arm: A64: Respect SPSEL when taking exceptions | Edgar E. Iglesias |
2014-06-09 | target-arm: A64: Implement CRC instructions | Peter Maydell |
2014-06-09 | target-arm: add support for v8 VMULL.P64 instruction | Peter Maydell |
2014-05-28 | tcg: Invert the inclusion of helper.h | Richard Henderson |
2014-05-27 | target-arm: A64: Introduce aarch64_banked_spsr_index() | Edgar E. Iglesias |
2014-05-27 | target-arm: c12_vbar -> vbar_el[] | Edgar E. Iglesias |
2014-05-27 | target-arm: Make esr_el1 an array | Edgar E. Iglesias |
2014-05-27 | target-arm: Make elr_el1 an array | Edgar E. Iglesias |
2014-04-17 | target-arm: Implement AArch64 EL1 exception handling | Rob Herring |
2014-03-17 | target-arm: A64: Implement FCVTXN | Peter Maydell |
2014-03-17 | target-arm: A64: Add FRECPX (reciprocal exponent) | Alex Bennée |
2014-03-17 | target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP | Peter Maydell |
2014-03-17 | target-arm: A64: Add remaining CLS/Z vector ops | Alex Bennée |
2014-03-17 | target-arm: A64: Implement PMULL instruction | Peter Maydell |
2014-02-20 | target-arm: A64: Implement remaining 3-same instructions | Peter Maydell |
2014-02-20 | target-arm: A64: Implement SIMD FP compare and set insns | Alex Bennée |
2014-02-20 | target-arm: A64: Implement plain vector SIMD indexed element insns | Peter Maydell |
2014-01-31 | target-arm: A64: Add SIMD TBL/TBLX | Michael Matz |
2014-01-08 | target-arm: A64: Add support for floating point compare | Claudio Fontana |
2013-12-17 | target-arm: A64: add support for 1-src CLS insn | Claudio Fontana |
2013-12-17 | target-arm: A64: add support for 1-src RBIT insn | Alexander Graf |
2013-12-17 | target-arm: A64: add support for 1-src data processing and CLZ | Claudio Fontana |
2013-12-17 | target-arm: A64: add support for 2-src data processing and DIV | Alexander Graf |
2013-12-17 | target-arm: A64: add stubs for a64 specific helpers | Alexander Graf |