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2024-09-20license: Update deprecated SPDX tag GPL-2.0 to GPL-2.0-onlyPhilippe Mathieu-Daudé
The 'GPL-2.0' license identifier has been deprecated since license list version 3.0 [1] and replaced by the 'GPL-2.0-only' tag [2]. [1] https://spdx.org/licenses/GPL-2.0.html [2] https://spdx.org/licenses/GPL-2.0-only.html Mechanical patch running: $ sed -i -e s/GPL-2.0/GPL-2.0-only/ \ $(git grep -l 'SPDX-License-Identifier: GPL-2.0[ $]' \ | egrep -v '^linux-headers|^include/standard-headers') Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-20license: Update deprecated SPDX tag GPL-2.0+ to GPL-2.0-or-laterPhilippe Mathieu-Daudé
The 'GPL-2.0+' license identifier has been deprecated since license list version 2.0rc2 [1] and replaced by the 'GPL-2.0-or-later' [2] tag. [1] https://spdx.org/licenses/GPL-2.0+.html [2] https://spdx.org/licenses/GPL-2.0-or-later.html Mechanical patch running: $ sed -i -e s/GPL-2.0+/GPL-2.0-or-later/ \ $(git grep -lP 'SPDX-License-Identifier: \W+GPL-2.0\+[ $]' \ | egrep -v '^linux-headers|^include/standard-headers') Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-20license: Update deprecated SPDX tag LGPL-2.0+ to LGPL-2.0-or-laterPhilippe Mathieu-Daudé
The 'LGPL-2.0+' license identifier has been deprecated since license list version 2.0rc2 [1] and replaced by the 'LGPL-2.0-or-later' [2] tag. [1] https://spdx.org/licenses/LGPL-2.0+.html [2] https://spdx.org/licenses/LGPL-2.0-or-later.html Mechanical patch running: $ sed -i -e s/LGPL-2.0+/LGPL-2.0-or-later/ \ $(git grep -l 'SPDX-License-Identifier: LGPL-2.0+$') Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-20license: Simplify GPL-2.0-or-later license descriptionsPhilippe Mathieu-Daudé
Since the "2 | 3+" expression can be simplified as "2+", it is pointless to mention the GPLv3 license. Add the corresponding SPDX identifier to remove all doubt. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-20util/cutils: Remove unused qemu_get_exec_dirDr. David Alan Gilbert
qemu_get_exec_dir has been unused since commit: 5bebe03f51 ("util/cutils: Clean up global variable shadowing in get_relocated_path()") Remove it, and fix up a comment that pointed to it. Signed-off-by: Dr. David Alan Gilbert <dave@treblig.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-20hw/sysbus: Remove unused sysbus_mmio_unmapDr. David Alan Gilbert
The last use of sysbus_mmio_unmap was removed by 981b1c6266 ("spapr/xive: rework the mapping the KVM memory regions") Remove it. Signed-off-by: Dr. David Alan Gilbert <dave@treblig.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-20envlist: Remove unused envlist_parseDr. David Alan Gilbert
envlist_parse, envlist_parse_set, envlist_parse_unset were added in 2009 but never used, see: 04a6dfebb6 ("linux-user: Add generic env variable handling") Remove them. Signed-off-by: Dr. David Alan Gilbert <dave@treblig.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-09-19plugins: add plugin API to read guest memoryRowan Hart
Signed-off-by: Rowan Hart <rowanbhart@gmail.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20240827215329.248434-2-rowanbhart@gmail.com> [AJB: tweaked cpu_memory_rw_debug call] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240916085400.1046925-17-alex.bennee@linaro.org>
2024-09-19plugins: extend API to get latest memory value accessedPierrick Bouvier
This value can be accessed only during a memory callback, using new qemu_plugin_mem_get_value function. Returned value can be extended when QEMU will support accesses wider than 128 bits. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1719 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2152 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Xingtao Yao <yaoxt.fnst@fujitsu.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20240724194708.1843704-3-pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240916085400.1046925-6-alex.bennee@linaro.org>
2024-09-19plugins: save value during memory accessesPierrick Bouvier
Different code paths handle memory accesses: - tcg generated code - load/store helpers - atomic helpers This value is saved in cpu->neg.plugin_mem_value_{high,low}. Values are written only for accessed word size (upper bits are not set). Atomic operations are doing read/write at the same time, so we generate two memory callbacks instead of one, to allow plugins to access distinct values. For now, we can have access only up to 128 bits, thus split this in two 64 bits words. When QEMU will support wider operations, we'll be able to reconsider this. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20240724194708.1843704-2-pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240916085400.1046925-5-alex.bennee@linaro.org>
2024-09-18mac_dbdma: Remove leftover `dma_memory_unmap` callsMattias Nissler
These were passing a NULL buffer pointer unconditionally, which happens to behave in a mostly benign way (except for the chance of an excess memory region unref and a bounce buffer leak). Per the function comment, this was never meant to be accepted though, and triggers an assertion with the "softmmu: Support concurrent bounce buffers" change. Given that the code in question never sets up any mappings, just remove the unnecessary dma_memory_unmap calls along with the DBDMA_io struct fields that are now entirely unused. Signed-off-by: Mattias Nissler <mnissler@rivosinc.com> Message-Id: <20240916175708.1829059-1-mnissler@rivosinc.com> Fixes: be1e343995 ("macio: switch over to new byte-aligned DMA helpers") Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2024-09-17Merge tag 'pull-request-2024-09-17' of https://gitlab.com/thuth/qemu into ↵Peter Maydell
staging * Make all qtest targets work with "--without-default-devices" * Replace assert(0) and assert(false) in qtests and s390x code * Enable the device aliases for or1k * Some other small test improvements # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmbpWwwRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbUj2A//VQwwbbuQa4FO/fu8mX0/iL43IZPLkVvC # XPesidMwEsaNlfnUGLwjr9/F9sU7NXSkEdBWshU69ER9D4FPvRlZ6xOc0GB2HHEm # 2zYBaQoMvB/g5/FMkp5/YqPc/FvYMxePTX0syJCUkdf9hbM3YJagUgSKaz/2ZJRu # +wztsRMSGx9WBeabTWgbAtGlfEqtfSGdfFHbNtoEVmO/K3rvcAHJhPXZpSmdq4CV # ymwYQ3Ul1Sdz/34TzshhkY9VvYU6n1zuB+kGrjPcQrOdBV/ukJuBiFkHfSZm/2ch # zTqbdXvkds867vHMo9s3JeVKPa8ZytKn4ycXXgVS5AZtrnEnyHztlVHWbwbHSafF # rVGXnE3FabzKL4sEKGzOjMegnwdWtpBNwMVKUZIgURqDXAVVR2m+lf2pW/Niz2WR # m0LNIcg0NPvxPwuq1xLVHc3CLNSCszu4Ao5YRhKimf3hb+FvzHty3dxn+DDg4+Q4 # hHqQRcbWILhYJEwcAVkfaMTtCh/RESiNi0U7Teqvr+aqBsJP8kdCkE5rY7cqzrqn # aDaompDZ8QG1QA1c3NaxtmNsvTvpm8gBySrqbMizo8UHQd85HDdXFkAZfI4HWKDi # jhZAEyh1HLeXrgDT/D0WBWQdPLjDZewTvqgqT/A5XbdR1u4XYXcxwMCpIN1iKFoY # 8qu0hIcsILM= # =DXEK # -----END PGP SIGNATURE----- # gpg: Signature made Tue 17 Sep 2024 11:33:48 BST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2024-09-17' of https://gitlab.com/thuth/qemu: .gitlab-ci.d/crossbuilds.yml: Force 'make check' to -j2 for cross-i686-tci tests/functional: Move the mips64el fuloong2e test into the thorough category docs/fuzz: fix outdated mention to enable-sanitizers system: Enable the device aliases for or1k, too system: Sort QEMU_ARCH_VIRTIO_PCI definition tests/qtest: remove break after g_assert_not_reached() tests/qtest: replace assert(false) with g_assert_not_reached() include/hw/s390x: replace assert(false) with g_assert_not_reached() tests/unit: replace assert(0) with g_assert_not_reached() tests/qtest: replace assert(0) with g_assert_not_reached() gitlab: fix logic for changing docker tag on stable branches .gitlab-ci.d/buildtest: Build most targets in the build-without-defaults job tests/qtest: Disable numa-test if the default machine is not available tests/qtest/meson.build: Add more CONFIG switches checks for the x86 tests tests/qtest/hd-geo-test: Check for availability of "pc" machine before using it tests/qtest/boot-order-test: Make the machine name mandatory in this test tests/qtest/cdrom-test: Improve the machine detection in the cdrom test Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-17include/hw/s390x: replace assert(false) with g_assert_not_reached()Pierrick Bouvier
This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Eric Farman <farman@linux.ibm.com> Message-ID: <20240912073921.453203-15-pierrick.bouvier@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-09-16hw/i2c/aspeed: Add support for Tx/Rx buffer 64 bit addressesJamin Lin
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) and the base address of dram is "0x4 00000000" which is 64bits address. It has "Master DMA Mode Tx Buffer Base Address[39:32](0x60)" and "Master DMA Mode Rx Buffer Base Address[39:32](0x64)" registers to save the high part physical address of Tx/Rx buffer address for master mode. It has "Slave DMA Mode Tx Buffer Base Address[39:32](0x68)" and "Slave DMA Mode Rx Buffer Base Address[39:32](0x6C)" registers to save the high part physical address of Tx/Rx buffer address for slave mode. Ex: Tx buffer address for master mode [39:0] The "Master DMA Mode Tx Buffer Base Address[39:32](0x60)" bits [7:0] which corresponds the bits [39:32] of the 64 bits address of the Tx buffer address. The "Master DMA Mode Tx Buffer Base Address(0x30)" bits [31:0] which corresponds the bits [31:0] of the 64 bits address of the Tx buffer address. Introduce a new has_dma64 class attribute and new registers for the new mode to support DMA 64 bits dram address. Update new mode register number to 28. The aspeed_i2c_bus_vmstate is changed again and version is not increased because it was done earlier in the same series. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
2024-09-16hw/i2c/aspeed: Add AST2700 supportJamin Lin
Introduce a new ast2700 class to support AST2700. The I2C bus register memory regions and I2C bus pool buffer memory regions are discontinuous and they do not back compatible AST2600. Add a new ast2700 i2c class init function to match the address of I2C bus register and pool buffer from the datasheet. An I2C controller registers owns 8KB address space. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-09-16hw/i2c/aspeed: Introduce a new dma_dram_offset attribute in AspeedI2CbusJamin Lin
The "Current DMA Operating Address Status(0x50)" register of I2C new mode has been removed in AST2700. This register is used for debugging and it is a read only register. To support AST2700 DMA mode, introduce a new dma_dram_offset class attribute in AspeedI2Cbus to save the current DMA operating address. ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 00000000" which is 64bits address. Set the dma_dram_offset data type to uint64_t for 64 bits dram address DMA support. Both "DMA Mode Buffer Address Register(I2CD24 old mode)" and "DMA Operating Address Status (I2CC50 new mode)" are used for showing the low part dram offset bits [31:0], so change to read/write both register bits [31:0] in bus register read/write functions. The aspeed_i2c_bus_vmstate is changed again and version is not increased because it was done earlier in the same series. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-09-16hw/i2c/aspeed: Support discontinuous poll buffer memory region of I2C busJamin Lin
It only support continuous pool buffer memory region for all I2C bus. However, the pool buffer address of all I2c bus are discontinuous for AST2700. Ex: the pool buffer address of I2C bus for ast2700 as following. 0x1A0 - 0x1BF: Device 0 buffer 0x2A0 - 0x2BF: Device 1 buffer 0x3A0 - 0x3BF: Device 2 buffer 0x4A0 - 0x4BF: Device 3 buffer 0x5A0 - 0x5BF: Device 4 buffer 0x6A0 - 0x6BF: Device 5 buffer 0x7A0 - 0x7BF: Device 6 buffer 0x8A0 - 0x8BF: Device 7 buffer 0x9A0 - 0x9BF: Device 8 buffer 0xAA0 - 0xABF: Device 9 buffer 0xBA0 - 0xBBF: Device 10 buffer 0xCA0 - 0xCBF: Device 11 buffer 0xDA0 - 0xDBF: Device 12 buffer 0xEA0 - 0xEBF: Device 13 buffer 0xFA0 – 0xFBF: Device 14 buffer 0x10A0 – 0x10BF: Device 15 buffer Introduce a new class attribute to make user set each I2C bus pool buffer gap size. Update formula to create all I2C bus pool buffer memory regions. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-09-16hw/i2c/aspeed: Introduce a new bus pool buffer attribute in AspeedI2CbusJamin Lin
According to the datasheet of ASPEED SOCs, each I2C bus has their own pool buffer since AST2500. Only AST2400 utilized a pool buffer share to all I2C bus. Besides, using a share pool buffer only support pool buffer memory regions are continuous for all I2C bus. To make this model more readable and support discontinuous bus pool buffer memory regions, changes to introduce a new bus pool buffer attribute in AspeedI2Cbus and new memops. So, it does not need to calculate the pool buffer offset for different I2C bus. Introduce a new has_share_pool class attribute in AspeedI2CClass and use it to create either a share pool buffer or bus pool buffers in aspeed_i2c_realize. Update each pull buffer size to 0x10 for AST2500 and 0x20 for AST2600 and AST1030. Incrementing the version of aspeed_i2c_bus_vmstate to 6. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-09-16hw/i2c/aspeed: Support discontinuous register memory region of I2C busJamin Lin
It only support continuous register memory region for all I2C bus. However, the register address of all I2c bus are discontinuous for AST2700. Ex: the register address of I2C bus for ast2700 as following. 0x100 - 0x17F: Device 0 0x200 - 0x27F: Device 1 0x300 - 0x37F: Device 2 0x400 - 0x47F: Device 3 0x500 - 0x57F: Device 4 0x600 - 0x67F: Device 5 0x700 - 0x77F: Device 6 0x800 - 0x87F: Device 7 0x900 - 0x97F: Device 8 0xA00 - 0xA7F: Device 9 0xB00 - 0xB7F: Device 10 0xC00 - 0xC7F: Device 11 0xD00 - 0xD7F: Device 12 0xE00 - 0xE7F: Device 13 0xF00 – 0xF7F: Device 14 0x1000 – 0x107F: Device 15 Introduce a new class attribute to make user set each I2C bus gap size. Update formula to create all I2C bus register memory regions. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-09-13ui/sdl2: ignore GUI keys in SDL_TEXTINPUT handlerVolker Rümelin
Ignore GUI keys for SDL_TEXTINPUT events, just like GUI keys are ignored for SDL_KEYDOWN events. This prevents unintended text input in a text console when hiding the text console with the GUI keys. The SDL_TEXTINPUT event always comes after the SDL_KEYDOWN event. See https://github.com/libsdl-org/SDL/issues/1659. Tested-by: Howard Spoelstra <hsp.cat7@gmail.com> Signed-off-by: Volker Rümelin <vr_qemu@t-online.de> Tested-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20240909061552.6122-3-vr_qemu@t-online.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-09-13ui/sdl2: release all modifiersVolker Rümelin
Each virtual console in the SDL2 frontend has a key state map. When switching windows with GUI keys we have to release all pressed modifier keys in the currently active window, because after the switch the now inactive window no longer receives the key release events. To reproduce the issue open a text editor in the SDL UI and then press Ctrl-Alt-2 to open a Compat Monitor Console. Close the console with the mouse. Try to enter text in the text editor and notice that the modifier keys Ctrl and Alt are stuck and need to be pressed once to be released. Tested-by: Howard Spoelstra <hsp.cat7@gmail.com> Signed-off-by: Volker Rümelin <vr_qemu@t-online.de> Tested-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20240909061552.6122-2-vr_qemu@t-online.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-09-13hw/char/escc: convert Sun mouse to use QemuInputHandlerMark Cave-Ayland
Update the Sun mouse implementation to use QemuInputHandler instead of the legacy qemu_add_mouse_event_handler() function. Note that this conversion adds extra sunmouse_* members to ESCCChannelState but they are not added to the migration stream (similar to the Sun keyboard members). If this were desired in future, the Sun devices should be split into separate devices and added to the migration stream there instead. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2518 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Carl Hauser <chauser@pullman.com> Message-ID: <20240904102301.175706-1-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-09-13fifo8: introduce fifo8_peek() functionMark Cave-Ayland
This allows uses to peek the byte at the current head of the FIFO. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Octavian Purdila <tavip@google.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240828122258.928947-9-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-09-13fifo8: add fifo8_peek_buf() functionMark Cave-Ayland
This is a wrapper function around fifo8_peekpop_buf() that allows the caller to peek into the FIFO, including handling the case where there is a wraparound of the internal FIFO buffer. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Octavian Purdila <tavip@google.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240828122258.928947-8-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-09-13hw/char/pl011: Remove unused 'readbuff' fieldPhilippe Mathieu-Daudé
Since its introduction in commit cdbdb648b7 ("ARM Versatile Platform Baseboard emulation.") PL011State::readbuff as never been used. Remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20240719181041.49545-3-philmd@linaro.org>
2024-09-13target/cris: Remove the deprecated CRIS targetPhilippe Mathieu-Daudé
The CRIS target is deprecated since v9.0 (commit c7bbef40234 "docs: mark CRIS support as deprecated"). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-ID: <20240904143603.52934-14-philmd@linaro.org>
2024-09-13system: Remove support for CRIS targetPhilippe Mathieu-Daudé
We are about to remove the CRIS target, so remove the sysemu part. This remove the CRIS 'none' machine. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-ID: <20240904143603.52934-13-philmd@linaro.org>
2024-09-13hw/dma: Remove ETRAX_FS DMA devicePhilippe Mathieu-Daudé
We just removed the single machine calling etraxfs_dmac_init() (the axis-dev88 machine). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-ID: <20240904143603.52934-11-philmd@linaro.org>
2024-09-13hw/net: Remove TYPE_ETRAX_FS_ETH devicePhilippe Mathieu-Daudé
We just removed the single machine using it (axis-dev88). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-ID: <20240904143603.52934-10-philmd@linaro.org>
2024-09-13hw/char: Remove TYPE_ETRAX_FS_SERIAL devicePhilippe Mathieu-Daudé
We just removed the single machine using it (axis-dev88). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-ID: <20240904143603.52934-9-philmd@linaro.org>
2024-09-13linux-user: Remove support for CRIS targetPhilippe Mathieu-Daudé
As per the deprecation notice in commit c7bbef4023: The CRIS architecture was pulled from Linux in 4.17 and the compiler is no longer packaged in any distro making it harder to run the `check-tcg` tests. Unless we can improve the testing situation there is a chance the code will bitrot without anyone noticing. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-ID: <20240904143603.52934-5-philmd@linaro.org>
2024-09-13hw/sh4: Remove sh7750_register_io_device() helperPhilippe Mathieu-Daudé
sh7750_register_io_device() was only used by the TC58128 NAND EEPROM which has been removed in the previous commit. Remove it as unused code. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-ID: <20240903153959.18392-4-philmd@linaro.org>
2024-09-13hw/block: Remove TC58128 NAND EEPROMPhilippe Mathieu-Daudé
The TC58128 NAND EEPROM is not user creatable and needs to be instanciated in the code via tc58128_init(). Only the SHIX machine was using it, and it was removed in the previous commit. Since the TC58128 has no more users, remove it too. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240903153959.18392-3-philmd@linaro.org>
2024-09-13hw/pci-host/designware: Declare CPU QOM types using DEFINE_TYPES() macroPhilippe Mathieu-Daudé
When multiple QOM types are registered in the same file, it is simpler to use the the DEFINE_TYPES() macro. In particular because type array declared with such macro are easier to review. Remove a pointless structure declaration in "designware.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Message-Id: <20231012121857.31873-2-philmd@linaro.org>
2024-09-13hvf: Split up hv_vm_create logic per archDanny Canter
This is preliminary work to split up hv_vm_create logic per platform so we can support creating VMs with > 64GB of RAM on Apple Silicon machines. This is done via ARM HVF's hv_vm_config_create() (and other APIs that modify this config that will be coming in future patches). This should have no behavioral difference at all as hv_vm_config_create() just assigns the same default values as if you just passed NULL to the function. Signed-off-by: Danny Canter <danny_canter@apple.com> Message-id: 20240828111552.93482-3-danny_canter@apple.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-13hw/boards: Add hvf_get_physical_address_range to MachineClassDanny Canter
This addition will be necessary for some HVF related work to follow. For HVF on ARM there exists a set of APIs in macOS 13 to be able to adjust the IPA size for a given VM. This is useful as by default HVF uses 36 bits as the IPA size, so to support guests with > 64GB of RAM we'll need to reach for this. To have all the info necessary to carry this out however, we need some plumbing to be able to grab the memory map and compute the highest GPA prior to creating the VM. This is almost exactly like what kvm_type is used for on ARM today, and is also what this will be used for. We will compute the highest GPA and find what IPA size we'd need to satisfy this, and if it's valid (macOS today caps at 40b) we'll set this to be the IPA size in coming patches. This new method is only needed (today at least) on ARM, and obviously only for HVF/macOS, so admittedly it is much less generic than kvm_type today, but it seemed a somewhat sane way to get the information we need from the memmap at VM creation time. Signed-off-by: Danny Canter <danny_canter@apple.com> Message-id: 20240828111552.93482-2-danny_canter@apple.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: removed explicit setting of field to NULL on x86] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-13kvm: Use 'unsigned long' for request argument in functions wrapping ioctl()Johannes Stoelp
Change the data type of the ioctl _request_ argument from 'int' to 'unsigned long' for the various accel/kvm functions which are essentially wrappers around the ioctl() syscall. The correct type for ioctl()'s 'request' argument is confused: * POSIX defines the request argument as 'int' * glibc uses 'unsigned long' in the prototype in sys/ioctl.h * the glibc info documentation uses 'int' * the Linux manpage uses 'unsigned long' * the Linux implementation of the syscall uses 'unsigned int' If we wrap ioctl() with another function which uses 'int' as the type for the request argument, then requests with the 0x8000_0000 bit set will be sign-extended when the 'int' is cast to 'unsigned long' for the call to ioctl(). On x86_64 one such example is the KVM_IRQ_LINE_STATUS request. Bit requests with the _IOC_READ direction bit set, will have the high bit set. Fortunately the Linux Kernel truncates the upper 32bit of the request on 64bit machines (because it uses 'unsigned int', and see also Linus Torvalds' comments in https://sourceware.org/bugzilla/show_bug.cgi?id=14362 ) so this doesn't cause active problems for us. However it is more consistent to follow the glibc ioctl() prototype when we define functions that are essentially wrappers around ioctl(). This resolves a Coverity issue where it points out that in kvm_get_xsave() we assign a value (KVM_GET_XSAVE or KVM_GET_XSAVE2) to an 'int' variable which can't hold it without overflow. Resolves: Coverity CID 1547759 Signed-off-by: Johannes Stoelp <johannes.stoelp@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 20240815122747.3053871-1-peter.maydell@linaro.org [PMM: Rebased patch, adjusted commit message, included note about Coverity fix, updated the type of the local var in kvm_get_xsave, updated the comment in the KVMState struct definition] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-13hw/core/resettable: Remove transitional_function machineryPeter Maydell
We used to need the transitional_function machinery to handle bus classes and device classes which still used their legacy reset handling. We have now converted all bus classes to three phase reset, and simplified the device class legacy reset so it is just an adapting wrapper function around registration of a hold phase method. There are therefore no more users of the transitional_function machinery and we can remove it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240830145812.1967042-12-peter.maydell@linaro.org
2024-09-13hw: Rename DeviceClass::reset field to legacy_resetPeter Maydell
Rename the DeviceClass::reset field to legacy_reset; this is helpful both in flagging up that it's best not used in new code and in making it easy to search for where it's being used still. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240830145812.1967042-9-peter.maydell@linaro.org
2024-09-13hw: Define new device_class_set_legacy_reset()Peter Maydell
Define a device_class_set_legacy_reset() function which sets the DeviceClass::reset field. This serves two purposes: * it makes it clearer to the person writing code that DeviceClass::reset is now legacy and they should look for the new alternative (which is Resettable) * it makes it easier to rename the reset field (which in turn makes it easier to find places that call it) The Coccinelle script can be used to automatically convert code that was doing an open-coded assignment to DeviceClass::reset to call device_class_set_legacy_reset() instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240830145812.1967042-7-peter.maydell@linaro.org
2024-09-13hw: Remove device_class_set_parent_reset()Peter Maydell
There are no callers of device_class_set_parent_reset() left in the tree, as they've all been converted to use three-phase reset and the corresponding resettable_class_set_parent_phases() function. Remove device_class_set_parent_reset(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240830145812.1967042-5-peter.maydell@linaro.org
2024-09-13target/s390: Convert CPU to Resettable interfacePeter Maydell
Convert the s390 CPU to the Resettable interface. This is slightly more involved than the other CPU types were (see commits 9130cade5fc22..d66e64dd006df) because S390 has its own set of different kinds of reset with different behaviours that it needs to trigger. We handle this by adding these reset types to the Resettable ResetType enum. Now instead of having an underlying implementation of reset that is s390-specific and which might be called either directly or via the DeviceClass::reset method, we can implement only the Resettable hold phase method, and have the places that need to trigger an s390-specific reset type do so by calling resettable_reset(). The other option would have been to smuggle in the s390 reset type via, for instance, a field in the CPU state that we set in s390_do_cpu_initial_reset() etc and then examined in the reset method, but doing it this way seems cleaner. The motivation for this change is that this is the last caller of the legacy device_class_set_parent_reset() function, and removing that will let us clean up some glue code that we added for the transition to three-phase reset. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Message-id: 20240830145812.1967042-4-peter.maydell@linaro.org
2024-09-13Merge tag 'pull-loongarch-20240912' of https://gitlab.com/gaosong/qemu into ↵Peter Maydell
staging pull-loongarch-20240912 # -----BEGIN PGP SIGNATURE----- # # iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZuLmLgAKCRBAov/yOSY+ # 38JNA/9UdorT4a7H+H5PhNeEu2EHDgMPb7+gxyYKw03mOG2MB3KFzkK0LRQShaPt # ADJmIqAFlc9SJLkbo6ELMDl+ZnUU9OdC/P6YU5iBG71zx1PonMwuyJTWhlBwxWcG # +OB8aDBUALoe/Gb4za152I84cR08g58TgLnXNfEkCM8lnPfAug== # =Plwu # -----END PGP SIGNATURE----- # gpg: Signature made Thu 12 Sep 2024 14:01:34 BST # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20240912' of https://gitlab.com/gaosong/qemu: hw/loongarch: Add acpi SPCR table support hw/loongarch: virt: pass random seed to fdt hw/loongarch: virt: support up to 4 serial ports target/loongarch: Support QMP dump-guest-memory target/loongarch/kvm: Add vCPU reset function hw/loongarch: Remove default enable with VIRTIO_VGA device target/loongarch: Add compatible support about VM reboot Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-12Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Peter Maydell
into staging virtio,pc,pci: features, fixes, cleanups i286 acpi speedup by precomputing _PRT by Ricardo Ribalda vhost_net speedup by using MR transactions by Zuo Boqun ich9 gained support for periodic and swsmi timer by Dominic Prinz Fixes, cleanups all over the place. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmbhoCUPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRptpUH/iR5AmJFpvAItqlPOvJiYDEch46C73tyrSws # Kk/1EbGSL7mFFD5sfdSSV4Rw8CQBsmM/Dt5VDkJKsWnOLjkBQ2CYH0MYHktnrKcJ # LlSk32HnY5p1DsXnJhgm5M7St8T3mV/oFdJCJAFgCmpx5uT8IRLrKETN8+30OaiY # xo35xAKOAS296+xsWeVubKkMq7H4y2tdZLE/22gb8rlA8d96BJIeVLQ3y3IjeUPR # 24q6c7zpObzGhYNZ/PzAKOn+YcVsV/lLAzKRZJTzTUPyG24BcjJTyyr/zNSYAgfk # lLXzIZID3GThBmrCAiDZ1z6sfo3MRg2wNS/FBXtK6fPIuFxed+8= # =ySRy # -----END PGP SIGNATURE----- # gpg: Signature made Wed 11 Sep 2024 14:50:29 BST # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: hw/acpi/ich9: Add periodic and swsmi timer virtio-mem: don't warn about THP sizes on a kernel without THP support hw/audio/virtio-sound: fix heap buffer overflow hw/cxl: fix physical address field in get scan media results output virtio-pci: Add lookup subregion of VirtIOPCIRegion MR vhost_net: configure all host notifiers in a single MR transaction tests/acpi: pc: update golden masters for DSDT hw/i386/acpi-build: Return a pre-computed _PRT table tests/acpi: pc: allow DSDT acpi table changes intel_iommu: Make PASID-cache and PIOTLB type invalid in legacy mode intel_iommu: Fix invalidation descriptor type field virtio: rename virtio_split_packed_update_used_idx hw/pci/pci-hmp-cmds: Avoid displaying bogus size in 'info pci' pci: don't skip function 0 occupancy verification for devfn auto assign hw/isa/vt82c686.c: Embed i8259 irq in device state instead of allocating hw: Move declaration of IRQState to header and add init function virtio: Always reset vhost devices virtio: Allow .get_vhost() without vhost_started Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-12hw/loongarch: virt: support up to 4 serial portsJason A. Donenfeld
In order to support additional channels of communication using `-serial`, add several serial ports, up to the standard 4 generally supported by the 8250 driver. Fixed: https://lore.kernel.org/all/20240907143439.2792924-1-Jason@zx2c4.com/ Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Tested-by: Bibo Mao <maobibo@loongson.cn> [gaosong: ACPI uart need't reverse order] Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20240907143439.2792924-1-Jason@zx2c4.com>
2024-09-11hw/acpi/ich9: Add periodic and swsmi timerDominic Prinz
This patch implements the periodic and the swsmi ICH9 chipset timers. They are especially useful when prototyping UEFI firmware (e.g. with EDK2's OVMF) using QEMU. For backwards compatibility, the compat properties "x-smi-swsmi-timer", and "x-smi-periodic-timer" are introduced. Additionally, writes to the SMI_STS register are enabled for the corresponding two bits using a write mask to make future work easier. Signed-off-by: Dominic Prinz <git@dprinz.de> Message-Id: <1d90ea69e01ab71a0f2ced116801dc78e04f4448.1725991505.git.git@dprinz.de> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-09-11vhost_net: configure all host notifiers in a single MR transactionzuoboqun
This allows the vhost_net device which has multiple virtqueues to batch the setup of all its host notifiers. This significantly reduces the vhost_net device starting and stoping time, e.g. the time spend on enabling notifiers reduce from 630ms to 75ms and the time spend on disabling notifiers reduce from 441ms to 45ms for a VM with 192 vCPUs and 15 vhost-user-net devices (64vq per device) in our case. Signed-off-by: zuoboqun <zuoboqun@baidu.com> Message-Id: <20240816070835.8309-1-zuoboqun@baidu.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-09-11hw: Move declaration of IRQState to header and add init functionBALATON Zoltan
To allow embedding a qemu_irq in a struct move its definition to the header and add a function to init it in place without allocating it. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <e3ffd0f6ef8845d0f7247c9b6ff33f7ee8b432cf.1719690591.git.balaton@eik.bme.hu> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
2024-09-10virtio: Allow .get_vhost() without vhost_startedHanna Czenczek
Historically, .get_vhost() was probably only called when vdev->vhost_started is true. However, we now decidedly want to call it also when vhost_started is false, specifically so we can issue a reset to the vhost back-end while device operation is stopped. Some .get_vhost() implementations dereference some pointers (or return offsets from them) that are probably guaranteed to be non-NULL when vhost_started is true, but not necessarily otherwise. This patch makes all such implementations check all such pointers, returning NULL if any is NULL. Signed-off-by: Hanna Czenczek <hreitz@redhat.com> Message-Id: <20240723163941.48775-2-hreitz@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-09-10Merge tag 'pull-qapi-2024-09-10' of https://repo.or.cz/qemu/armbru into stagingPeter Maydell
QAPI patches patches for 2024-09-10 # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmbgS0ASHGFybWJydUBy # ZWRoYXQuY29tAAoJEDhwtADrkYZTm+sP/1kEuGdbjjVLQC7U+gCClhALpYUtIMHQ # qNZWmnxFyW9Jx6Lk8+FZBRJegNlmA9AJ2ZzD/2I/WoNtcrNiE53rIRG71Lcy8I6U # CRjekLPn0jhFuYhmRfwz6ilcLkyMJ15Yi7iG6ssFsO1joBtU5Q1qpzQmFUl9UbV9 # 9iBe7mE99VzNwi3hMELEM9YuSgAs8st4Itnn8SiHkJ3s6hlmF8N4HwNKfQrseGfb # FuJNN4p8Gcu0aF/dkGE8ADJBvtgzkFnavXt0GQPC7SjGOF7rUXxnUQlszNZM0OcK # UAfWU06sIyiOholQQt8H8jawT+rGCLomfgPUBVq5K8WByd21IeQeS0upSPeTjxS+ # d/C8wzpcbhdNOECwC/wDtgZHvCC95cHNrxuC4+4/Q1KIVVr+1cWqe8hQzFvm3TIg # dduEFTQDIxhpE0GO1ZWNf90upzBYBWwIsh4bqsMZS7SpaYIZ6QV45yViZ1w2WfbH # m3/F34Z3yqgFuZQrZv4OPo7xHK0+y7uZ60RrhSJtE0X080syRJKBbGmNBRidoVyu # JOONWH44I/XN5enZV8StJnqJr9MCV0DBZUCi9ZhP/kAhBjLc5cQ6NByEa9/rebYX # 1bLTiA1JDLzDVIan+A8dz0riWmHBvTyBwhLnEXvXb9lcB3ozgHTb7axE5RnZSYLI # YQgBOBMFuQKM # =YO/Q # -----END PGP SIGNATURE----- # gpg: Signature made Tue 10 Sep 2024 14:36:00 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * tag 'pull-qapi-2024-09-10' of https://repo.or.cz/qemu/armbru: qapi/vfio: Rename VfioMigrationState to Qapi*, and drop prefix qapi/cryptodev: Rename QCryptodevBackendAlgType to *Algo, and drop prefix qapi/cryptodev: Drop unwanted 'prefix' qapi/crypto: Rename QCryptoAFAlg to QCryptoAFAlgo qapi/crypto: Rename QCryptoRSAPaddingAlgorithm to *Algo, and drop prefix qapi/crypto: Rename QCryptoAkCipherAlgorithm to *Algo, and drop prefix qapi/crypto: Rename QCryptoIVGenAlgorithm to *Algo, and drop prefix qapi/crypto: Rename QCryptoCipherAlgorithm to *Algo, and drop prefix qapi/crypto: Rename QCryptoHashAlgorithm to *Algo, and drop prefix qapi/crypto: Drop unwanted 'prefix' qapi/machine: Rename CpuS390* to S390Cpu*, and drop 'prefix' qapi/ui: Drop temporary 'prefix' qapi/machine: Drop temporary 'prefix' qapi/ebpf: Drop temporary 'prefix' qapi/crypto: Drop temporary 'prefix' qapi/common: Drop temporary 'prefix' qapi/block-core: Drop temporary 'prefix' tests/qapi-schema: Drop temporary 'prefix' qapi: Smarter camel_to_upper() to reduce need for 'prefix' Signed-off-by: Peter Maydell <peter.maydell@linaro.org>