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path: root/include/hw/riscv
AgeCommit message (Expand)Author
2022-10-14hw/riscv: virt: Enable booting S-mode firmware from pflashSunil V L
2022-09-27hw/riscv/sifive_e: Fix inheritance of SiFiveEStateBernhard Beschow
2022-09-27hw/riscv: opentitan: Expose the resetvec as a SoC propertyAlistair Francis
2022-09-07hw/riscv: virt: fix the plic's address cellsConor Dooley
2022-09-07hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripheralsConor Dooley
2022-09-07hw/riscv: opentitan: bump opentitan versionWilfred Mallawa
2022-09-07hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()Daniel Henrique Barboza
2022-05-11Clean up header guards that don't match their file nameMarkus Armbruster
2022-04-29hw/riscv: virt: Create a platform busAlistair Francis
2022-04-29hw/riscv: virt: Add a machine done notifierAlistair Francis
2022-04-22hw/riscv: boot: Support 64bit fdt address.Dylan Jhong
2022-04-22riscv: opentitan: Connect opentitan SPI HostWilfred Mallawa
2022-03-03hw: riscv: opentitan: fixup SPI addressesWilfred Mallawa
2022-03-03hw/riscv: virt: Increase maximum number of allowed CPUsAnup Patel
2022-03-03hw/riscv: virt: Add optional AIA IMSIC support to virt machineAnup Patel
2022-03-03hw/riscv: virt: Add optional AIA APLIC support to virt machineAnup Patel
2022-01-21hw/riscv: Remove macros for ELF BIOS image namesAnup Patel
2022-01-21hw/riscv: spike: Allow using binary firmware as biosAnup Patel
2022-01-21target/riscv: Support start kernel directly by KVMYifei Jiang
2022-01-08hw/riscv: virt: Allow support for 32 coresAlistair Francis
2021-10-28hw/riscv: microchip_pfsoc: Use the PLIC config helper functionAlistair Francis
2021-10-28hw/riscv: sifive_u: Use the PLIC config helper functionAlistair Francis
2021-10-28hw/riscv: boot: Add a PLIC config string functionAlistair Francis
2021-10-28hw/riscv: virt: Don't use a macro for the PLIC configurationAlistair Francis
2021-10-22hw/riscv: opentitan: Update to the latest buildAlistair Francis
2021-09-21hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel
2021-09-21sifive_u: Connect the SiFive PWM deviceAlistair Francis
2021-07-15hw/riscv: opentitan: Add the flash aliasAlistair Francis
2021-07-15hw/riscv: opentitan: Add the unimplement rv_core_ibex_periAlistair Francis
2021-06-24hw/riscv: OpenTitan: Connect the mtime and mtimecmp timerAlistair Francis
2021-06-08hw/riscv: Use macros for BIOS image namesBin Meng
2021-05-11hw/opentitan: Update the interrupt layoutAlistair Francis
2021-05-11hw/riscv: Connect Shakti UART to Shakti platformVijai Kumar K
2021-05-11riscv: Add initial support for Shakti C machineVijai Kumar K
2021-03-22hw/riscv: microchip_pfsoc: Map EMMC/SD mux registerBin Meng
2021-03-22hw/riscv: Add fw_cfg support to virtAsherah Connor
2021-03-10hw/riscv: migrate fdt field to generic MachineStateAlex Bennée
2021-03-04hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal valueBin Meng
2021-03-04hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng
2021-03-04hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng
2021-01-16riscv: Pass RISCVHartArrayState by pointerAlistair Francis
2020-12-17riscv/opentitan: Update the OpenTitan memory layoutAlistair Francis
2020-12-17hw/riscv: Use the CPU to determine if 32-bitAlistair Francis
2020-12-17hw/riscv: boot: Remove compile time XLEN checksAlistair Francis
2020-12-17riscv: virt: Remove target macro conditionalsAlistair Francis
2020-12-17riscv: spike: Remove target macro conditionalsAlistair Francis
2020-12-17hw/riscv: microchip_pfsoc: add QSPI NOR flashVitaly Wool
2020-11-03hw/riscv: microchip_pfsoc: Hook the I2C1 controllerBin Meng
2020-11-03hw/riscv: microchip_pfsoc: Correct DDR memory mapBin Meng
2020-11-03hw/riscv: microchip_pfsoc: Map the reserved memory at address 0Bin Meng
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