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path: root/include/hw/riscv/opentitan.h
AgeCommit message (Expand)Author
2022-09-27hw/riscv: opentitan: Expose the resetvec as a SoC propertyAlistair Francis
2022-09-07hw/riscv: opentitan: bump opentitan versionWilfred Mallawa
2022-04-22riscv: opentitan: Connect opentitan SPI HostWilfred Mallawa
2022-03-03hw: riscv: opentitan: fixup SPI addressesWilfred Mallawa
2021-10-22hw/riscv: opentitan: Update to the latest buildAlistair Francis
2021-07-15hw/riscv: opentitan: Add the flash aliasAlistair Francis
2021-07-15hw/riscv: opentitan: Add the unimplement rv_core_ibex_periAlistair Francis
2021-06-24hw/riscv: OpenTitan: Connect the mtime and mtimecmp timerAlistair Francis
2021-05-11hw/opentitan: Update the interrupt layoutAlistair Francis
2020-12-17riscv/opentitan: Update the OpenTitan memory layoutAlistair Francis
2020-09-18Use OBJECT_DECLARE_SIMPLE_TYPE when possibleEduardo Habkost
2020-09-09Use DECLARE_*CHECKER* macrosEduardo Habkost
2020-09-09Move QOM typedefs and add missing includesEduardo Habkost
2020-08-27opentitan: Rename memmap enum constantsEduardo Habkost
2020-06-19riscv/opentitan: Connect the UART deviceAlistair Francis
2020-06-19riscv/opentitan: Connect the PLIC deviceAlistair Francis
2020-06-03riscv: Initial commit of OpenTitan machineAlistair Francis