| Age | Commit message (Expand) | Author |
|---|
| 2022-09-07 | hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals | Conor Dooley |
| 2021-10-28 | hw/riscv: microchip_pfsoc: Use the PLIC config helper function | Alistair Francis |
| 2021-03-22 | hw/riscv: microchip_pfsoc: Map EMMC/SD mux register | Bin Meng |
| 2020-12-17 | hw/riscv: microchip_pfsoc: add QSPI NOR flash | Vitaly Wool |
| 2020-11-03 | hw/riscv: microchip_pfsoc: Hook the I2C1 controller | Bin Meng |
| 2020-11-03 | hw/riscv: microchip_pfsoc: Correct DDR memory map | Bin Meng |
| 2020-11-03 | hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 | Bin Meng |
| 2020-11-03 | hw/riscv: microchip_pfsoc: Connect the SYSREG module | Bin Meng |
| 2020-11-03 | hw/riscv: microchip_pfsoc: Connect the IOSCB module | Bin Meng |
| 2020-11-03 | hw/riscv: microchip_pfsoc: Connect DDR memory controller modules | Bin Meng |
| 2020-09-09 | hw/riscv: microchip_pfsoc: Hook GPIO controllers | Bin Meng |
| 2020-09-09 | hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs | Bin Meng |
| 2020-09-09 | hw/riscv: microchip_pfsoc: Connect a DMA controller | Bin Meng |
| 2020-09-09 | hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card | Bin Meng |
| 2020-09-09 | hw/riscv: microchip_pfsoc: Connect 5 MMUARTs | Bin Meng |
| 2020-09-09 | hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board | Bin Meng |
