index
:
slackcoder/qemu
master
QEMU is a generic and open source machine & userspace emulator and virtualizer
Mirror
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
include
/
exec
Age
Commit message (
Expand
)
Author
2019-03-06
migration: Add an ability to ignore shared RAM blocks
Yury Kotov
2019-03-06
exec: Change RAMBlockIterFunc definition
Yury Kotov
2019-03-04
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
Peter Maydell
2019-02-21
include/exec/helper-head.h: support "const void *" in helper calls
David Hildenbrand
2019-02-21
vhost-net: compile it on all targets that have virtio-net.
Paolo Bonzini
2019-02-11
exec-all: document that tlb_fill can trigger a TLB resize
Emilio G. Cota
2019-02-07
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190206' into staging
Peter Maydell
2019-02-06
accel/tcg: Consider cluster index in tb_lookup__cpu_state()
Peter Maydell
2019-02-05
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
Peter Maydell
2019-02-05
exec: Add target-specific tlb bits to MemTxAttrs
Richard Henderson
2019-02-05
unify len and addr type for memory/address APIs
Li Zhijian
2019-01-29
accel/tcg: Add cluster number to TCG TB hash
Peter Maydell
2019-01-29
memory: add memory_region_flush_rom_device()
Stefan Hajnoczi
2019-01-28
cputlb: Remove static tlb sizing
Richard Henderson
2019-01-28
tcg: introduce dynamic TLB sizing
Emilio G. Cota
2019-01-11
qemu/queue.h: simplify reverse access to QTAILQ
Paolo Bonzini
2019-01-11
qemu/queue.h: leave head structs anonymous unless necessary
Paolo Bonzini
2018-12-26
tcg: Add TCG_CALL_NO_RETURN
Richard Henderson
2018-12-26
exec: Add RISC-V GCC poison macro
Alistair Francis
2018-12-17
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20181216' into staging
Peter Maydell
2018-12-17
include: move exec/tb-hash-xx.h to qemu/xxhash.h
Emilio G. Cota
2018-12-17
exec: introduce qemu_xxhash{2,4,5,6,7}
Emilio G. Cota
2018-12-14
Rename cpu_physical_memory_write_rom() to address_space_write_rom()
Peter Maydell
2018-11-06
memory: learn about non-volatile memory region
Marc-André Lureau
2018-10-31
cputlb: Remove tlb_c.pending_flushes
Richard Henderson
2018-10-31
cputlb: Filter flushes on already clean tlbs
Richard Henderson
2018-10-31
cputlb: Count "partial" and "elided" tlb flushes
Richard Henderson
2018-10-31
cputlb: Move env->vtlb_index to env->tlb_d.vindex
Richard Henderson
2018-10-31
cputlb: Split large page tracking per mmu_idx
Richard Henderson
2018-10-31
cputlb: Move cpu->pending_tlb_flush to env->tlb_c.pending_flush
Richard Henderson
2018-10-31
cputlb: Move tlb_lock to CPUTLBCommon
Richard Henderson
2018-10-30
Merge remote-tracking branch 'remotes/vivier2/tags/qemu-trivial-for-3.1-pull-...
Peter Maydell
2018-10-26
memory.h: fix typos in comments
Li Qiang
2018-10-25
target/mips: Add disassembler support for nanoMIPS
Aleksandar Markovic
2018-10-19
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
Peter Maydell
2018-10-19
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20181018' into staging
Peter Maydell
2018-10-19
target-i386 : add coalesced_pio API
Peng Hao
2018-10-19
COLO: Load dirty pages into SVM's RAM cache firstly
Zhang Chen
2018-10-18
cputlb: read CPUTLBEntry.addr_write atomically
Emilio G. Cota
2018-10-18
tcg: Add tlb_index and tlb_entry helpers
Richard Henderson
2018-10-18
cputlb: serialize tlb updates with env->tlb_lock
Emilio G. Cota
2018-10-18
exec: introduce tlb_init
Emilio G. Cota
2018-10-02
memory: Remove old_mmio accessors
Peter Maydell
2018-10-02
hostmem-file: make available memory-backend-file on POSIX-based hosts
Hikaru Nishida
2018-08-28
ppc: Remove deprecated ppcemb target
Thomas Huth
2018-08-21
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-3.1-pull-re...
Peter Maydell
2018-08-21
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
Peter Maydell
2018-08-20
memory: Remove MMIO request_ptr APIs
Peter Maydell
2018-08-17
linux-user: fix 32bit g2h()/h2g()
Laurent Vivier
2018-08-14
accel/tcg: Check whether TLB entry is RAM consistently with how we set it up
Peter Maydell
[next]