| Age | Commit message (Expand) | Author |
|---|
| 2020-06-22 | riscv/sifive_u: fix a memory leak in soc_realize() | Pan Nengyuan |
| 2019-11-25 | hw/riscv: Add optional symbol callback ptr to riscv_load_kernel() | Zhuang, Siwei (Data61, Kensington NSW) |
| 2019-11-25 | RISC-V: virt: This is a "sifive,test1" test finisher | Palmer Dabbelt |
| 2019-11-14 | riscv/virt: Increase flash size | Alistair Francis |
| 2019-10-28 | riscv/boot: Fix possible memory leak | Alistair Francis |
| 2019-10-28 | riscv/virt: Jump to pflash if specified | Alistair Francis |
| 2019-10-28 | riscv/virt: Add the PFlash CFI01 device | Alistair Francis |
| 2019-10-28 | riscv/virt: Manually define the machine | Alistair Francis |
| 2019-10-28 | riscv/sifive_u: Add the start-in-flash property | Alistair Francis |
| 2019-10-28 | riscv/sifive_u: Manually define the machine | Alistair Francis |
| 2019-10-28 | riscv/sifive_u: Add QSPI memory region | Alistair Francis |
| 2019-10-28 | riscv/sifive_u: Add L2-LIM cache memory | Alistair Francis |
| 2019-10-28 | riscv: sifive_u: Add ethernet0 to the aliases node | Bin Meng |
| 2019-10-28 | riscv: hw: Drop "clock-frequency" property of cpu nodes | Bin Meng |
| 2019-09-17 | riscv: sifive_u: Update model and compatible strings in device tree | Bin Meng |
| 2019-09-17 | riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet | Bin Meng |
| 2019-09-17 | riscv: sifive_u: Fix broken GEM support | Bin Meng |
| 2019-09-17 | riscv: sifive_u: Instantiate OTP memory with a serial number | Bin Meng |
| 2019-09-17 | riscv: sifive: Implement a model for SiFive FU540 OTP | Bin Meng |
| 2019-09-17 | riscv: sifive_u: Change UART node name in device tree | Bin Meng |
| 2019-09-17 | riscv: sifive_u: Update UART base addresses and IRQs | Bin Meng |
| 2019-09-17 | riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes | Bin Meng |
| 2019-09-17 | riscv: sifive_u: Add PRCI block to the SoC | Bin Meng |
| 2019-09-17 | riscv: sifive_u: Generate hfclk and rtcclk nodes | Bin Meng |
| 2019-09-17 | riscv: sifive: Implement PRCI model for FU540 | Bin Meng |
| 2019-09-17 | riscv: sifive_u: Update PLIC hart topology configuration string | Bin Meng |
| 2019-09-17 | riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC | Bin Meng |
| 2019-09-17 | riscv: sifive_u: Set the minimum number of cpus to 2 | Bin Meng |
| 2019-09-17 | riscv: hart: Add a "hartid-base" property to RISC-V hart array | Bin Meng |
| 2019-09-17 | riscv: hart: Extract hart realize to a separate routine | Bin Meng |
| 2019-09-17 | riscv: sifive_e: Drop sifive_mmio_emulate() | Bin Meng |
| 2019-09-17 | riscv: sifive_e: prci: Update the PRCI register block size | Bin Meng |
| 2019-09-17 | riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming | Bin Meng |
| 2019-09-17 | riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} | Bin Meng |
| 2019-09-17 | riscv: sifive_u: Remove the unnecessary include of prci header | Bin Meng |
| 2019-09-17 | riscv: hw: Remove the unnecessary include of target/riscv/cpu.h | Bin Meng |
| 2019-09-17 | riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead | Bin Meng |
| 2019-09-17 | riscv: hw: Change create_fdt() to return void | Bin Meng |
| 2019-09-17 | riscv: hw: Remove not needed PLIC properties in device tree | Bin Meng |
| 2019-09-17 | riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell | Bin Meng |
| 2019-09-17 | riscv: hw: Remove superfluous "linux, phandle" property | Bin Meng |
| 2019-09-17 | riscv: hw: Remove duplicated "hw/hw.h" inclusion | Bin Meng |
| 2019-09-17 | riscv: sifive_test: Add reset functionality | Bin Meng |
| 2019-09-17 | riscv: Resolve full path of the given bios image | Bin Meng |
| 2019-09-17 | riscv: Add a helper routine for finding firmware | Bin Meng |
| 2019-09-17 | riscv: plic: Remove unused interrupt functions | Alistair Francis |
| 2019-09-17 | riscv: sifive_u: Fix clock-names property for ethernet node | Guenter Roeck |
| 2019-09-17 | riscv: sivive_u: Add dummy serial clock and aliases entry for uart | Guenter Roeck |
| 2019-09-17 | riscv: sifive_u: Add support for loading initrd | Guenter Roeck |
| 2019-08-16 | Include sysemu/sysemu.h a lot less | Markus Armbruster |
