Age | Commit message (Expand) | Author |
2020-06-03 | riscv: Initial commit of OpenTitan machine | Alistair Francis |
2020-06-03 | riscv: sifive_e: Manually define the machine | Alistair Francis |
2020-06-03 | hw/riscv: spike: Remove deprecated ISA specific machines | Alistair Francis |
2020-06-03 | hw/riscv: virt: Remove the riscv_ prefix of the machine* functions | Bin Meng |
2020-06-03 | hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions | Bin Meng |
2020-06-03 | riscv: Change the default behavior if no -bios option is specified | Bin Meng |
2020-06-03 | riscv: Suppress the error report for QEMU testing with riscv_find_firmware() | Bin Meng |
2020-05-18 | hw: Use QEMU_IS_ALIGNED() on parallel flash block size | Philippe Mathieu-Daudé |
2020-05-15 | qom: Drop parameter @errp of object_property_add() & friends | Markus Armbruster |
2020-05-15 | qom: Drop object_property_set_description() parameter @errp | Markus Armbruster |
2020-04-29 | hw/riscv/spike: Allow more than one CPUs | Anup Patel |
2020-04-29 | hw/riscv/spike: Allow loading firmware separately using -bios option | Anup Patel |
2020-04-29 | hw/riscv: Add optional symbol callback ptr to riscv_load_firmware() | Anup Patel |
2020-04-29 | riscv: sifive_e: Support changing CPU type | Corey Wharton |
2020-04-29 | hw/riscv: Generate correct "mmu-type" for 32-bit machines | Bin Meng |
2020-04-29 | riscv/sifive_u: Add a serial property to the sifive_u machine | Bin Meng |
2020-04-29 | riscv/sifive_u: Add a serial property to the sifive_u SoC | Alistair Francis |
2020-04-29 | riscv/sifive_u: Fix up file ordering | Alistair Francis |
2020-04-29 | various: Remove suspicious '\' character outside of #define in C code | Philippe Mathieu-Daudé |
2020-03-17 | Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging | Peter Maydell |
2020-03-17 | hw/riscv: Let devices own the MemoryRegion they create | Philippe Mathieu-Daudé |
2020-03-17 | hw/riscv: Use memory_region_init_rom() with read-only regions | Philippe Mathieu-Daudé |
2020-03-16 | riscv: sifive_u: Update BIOS_FILENAME for 32-bit | Bin Meng |
2020-03-03 | Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf3' i... | Peter Maydell |
2020-02-28 | hw: Make MachineClass::is_default a boolean type | Philippe Mathieu-Daudé |
2020-02-27 | hw/riscv: Provide rdtime callback for TCG in CLINT emulation | Anup Patel |
2020-02-27 | riscv: virt: Allow PCI address 0 | Bin Meng |
2020-02-10 | riscv: virt: Use Goldfish RTC device | Anup Patel |
2020-02-10 | riscv/virt: Add syscon reboot and poweroff DT nodes | Anup Patel |
2020-01-29 | hw/core/loader: Let load_elf() populate a field with CPU-specific flags | Aleksandar Markovic |
2020-01-27 | Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging | Peter Maydell |
2020-01-24 | qdev: set properties with device_class_set_props() | Marc-André Lureau |
2020-01-16 | riscv/sifive_u: fix a memory leak in soc_realize() | Pan Nengyuan |
2020-01-08 | chardev: Use QEMUChrEvent enum in IOEventHandler typedef | Philippe Mathieu-Daudé |
2019-11-25 | hw/riscv: Add optional symbol callback ptr to riscv_load_kernel() | Zhuang, Siwei (Data61, Kensington NSW) |
2019-11-25 | RISC-V: virt: This is a "sifive,test1" test finisher | Palmer Dabbelt |
2019-11-14 | riscv/virt: Increase flash size | Alistair Francis |
2019-10-28 | riscv/boot: Fix possible memory leak | Alistair Francis |
2019-10-28 | riscv/virt: Jump to pflash if specified | Alistair Francis |
2019-10-28 | riscv/virt: Add the PFlash CFI01 device | Alistair Francis |
2019-10-28 | riscv/virt: Manually define the machine | Alistair Francis |
2019-10-28 | riscv/sifive_u: Add the start-in-flash property | Alistair Francis |
2019-10-28 | riscv/sifive_u: Manually define the machine | Alistair Francis |
2019-10-28 | riscv/sifive_u: Add QSPI memory region | Alistair Francis |
2019-10-28 | riscv/sifive_u: Add L2-LIM cache memory | Alistair Francis |
2019-10-28 | riscv: sifive_u: Add ethernet0 to the aliases node | Bin Meng |
2019-10-28 | riscv: hw: Drop "clock-frequency" property of cpu nodes | Bin Meng |
2019-09-17 | riscv: sifive_u: Update model and compatible strings in device tree | Bin Meng |
2019-09-17 | riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet | Bin Meng |
2019-09-17 | riscv: sifive_u: Fix broken GEM support | Bin Meng |