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path: root/hw/riscv/sifive_uart.c
AgeCommit message (Expand)Author
2020-09-09hw/riscv: Move sifive_uart model to hw/charBin Meng
2020-01-08chardev: Use QEMUChrEvent enum in IOEventHandler typedefPhilippe Mathieu-Daudé
2019-09-17riscv: hw: Remove the unnecessary include of target/riscv/cpu.hBin Meng
2019-09-17riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) insteadBin Meng
2019-08-16Include hw/hw.h exactly where neededMarkus Armbruster
2019-08-16Include hw/irq.h a lot lessMarkus Armbruster
2019-03-19riscv: sifive_uart: Generate TX interruptBin Meng
2018-12-20sifive_uart: Implement interrupt pending registerNathaniel Graff
2018-03-07SiFive RISC-V UART DeviceMichael Clark