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path: root/hw/riscv/sifive_u.c
AgeCommit message (Expand)Author
2022-05-24hw/riscv/sifive_u: Resolve redundant property accessorsBernhard Beschow
2022-05-24hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)Tsukasa OI
2022-04-29hw/riscv: Don't add empty bootargs to device treeBin Meng
2022-01-08hw/riscv: Use error_fatal for SoC realisationAlistair Francis
2021-12-15hw: Replace trivial drive_get_next() by drive_get()Markus Armbruster
2021-12-15hw/sd/ssi-sd: Do not create SD card within controller's realizeMarkus Armbruster
2021-10-28hw/riscv: sifive_u: Use the PLIC config helper functionAlistair Francis
2021-10-22hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_idBin Meng
2021-09-21hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel
2021-09-21hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel
2021-09-21sifive_u: Connect the SiFive PWM deviceAlistair Francis
2021-09-21hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis
2021-08-26arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell
2021-07-15hw/riscv: sifive_u: Make sure firmware info is 8-byte alignedBin Meng
2021-07-15hw/riscv: sifive_u: Correct the CLINT timebase frequencyBin Meng
2021-06-08hw/riscv: Use macros for BIOS image namesBin Meng
2021-06-08hw/riscv: Support the official PLIC DT bindingsBin Meng
2021-06-08hw/riscv: Support the official CLINT DT bindingsBin Meng
2021-06-08hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helperBin Meng
2021-05-02hw: Do not include qemu/log.h if it is not necessaryThomas Huth
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng
2021-03-04hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng
2021-03-04hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng
2021-01-16riscv: Pass RISCVHartArrayState by pointerAlistair Francis
2021-01-16hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_typeBin Meng
2020-12-17hw/riscv: Use the CPU to determine if 32-bitAlistair Francis
2020-12-17hw/riscv: sifive_u: Remove compile time XLEN checksAlistair Francis
2020-12-17hw/riscv: boot: Remove compile time XLEN checksAlistair Francis
2020-12-17hw/riscv: sifive_u: Add UART1 DT node in the generated DTBAnup Patel
2020-12-15vl: make qemu_get_machine_opts staticPaolo Bonzini
2020-11-03hw/riscv: sifive_u: Allow passing custom DTBAnup Patel
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis
2020-10-22hw/riscv: sifive_u: Allow specifying the CPUAlistair Francis
2020-09-22sifive_u: Register "start-in-flash" as class propertyEduardo Habkost
2020-09-18sifive_u: Rename memmap enum constantsEduardo Habkost
2020-09-09hw/riscv: Move sifive_uart model to hw/charBin Meng
2020-09-09hw/riscv: Move sifive_plic model to hw/intcBin Meng
2020-09-09hw/riscv: Move sifive_clint model to hw/intcBin Meng
2020-09-09hw/riscv: sifive_u: Connect a DMA controllerBin Meng
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng
2020-09-09target/riscv: cpu: Set reset vector based on the configured property valueBin Meng
2020-08-25hw/riscv: Allow creating multiple instances of PLICAnup Patel
2020-08-25hw/riscv: Allow creating multiple instances of CLINTAnup Patel
2020-08-21hw/riscv: Use pre-built bios image of generic platform for virt & sifive_uBin Meng
2020-08-21hw/riscv: sifive_u: Add a dummy L2 cache controller deviceBin Meng
2020-07-21hw: Mark nd_table[] misuse in realize methods FIXMEMarkus Armbruster
2020-07-13hw/riscv: Modify MROM size to end at 0x10000Bin Meng
2020-07-13RISC-V: Support 64 bit start addressAtish Patra
2020-07-13riscv: Add opensbi firmware dynamic supportAtish Patra
2020-07-13RISC-V: Copy the fdt in dram instead of ROMAtish Patra
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