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path: root/hw/riscv/sifive_plic.c
AgeCommit message (Expand)Author
2020-01-24qdev: set properties with device_class_set_props()Marc-André Lureau
2019-09-17riscv: plic: Remove unused interrupt functionsAlistair Francis
2019-08-16Include hw/qdev-properties.h lessMarkus Armbruster
2019-07-05hw/riscv: Replace global smp variables with machine smp propertiesLike Xu
2019-06-12Include qemu/module.h where needed, drop it from qemu-common.hMarkus Armbruster
2019-04-04riscv: plic: Log guest errorsAlistair Francis
2019-04-04riscv: plic: Fix incorrect irq calculationAlistair Francis
2019-03-28Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
2019-03-19RISC-V: Allow interrupt controllers to claim interruptsMichael Clark
2019-03-19RISC-V: Replace __builtin_popcount with ctpop8 in PLICMichael Clark
2019-03-18riscv: plic: Set msi_nonbroken as trueAlistair Francis
2018-12-20RISC-V: Fix PLIC pending bitfield readsMichael Clark
2018-10-17RISC-V: Allow setting and clearing multiple irqsMichael Clark
2018-09-04RISC-V: Use atomic_cmpxchg to update PLIC bitmapsMichael Clark
2018-07-05hw/riscv/sifive_plic: Use gpios instead of irqsAlistair Francis
2018-03-07SiFive RISC-V PLIC BlockMichael Clark