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path: root/hw/riscv/Kconfig
AgeCommit message (Expand)Author
2020-11-03hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng
2020-11-03hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng
2020-11-03hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng
2020-09-09hw/riscv: Sort the Kconfig options in alphabetical orderBin Meng
2020-09-09hw/riscv: Drop CONFIG_SIFIVEBin Meng
2020-09-09hw/riscv: Always build riscv_hart.cBin Meng
2020-09-09hw/riscv: Move sifive_test model to hw/miscBin Meng
2020-09-09hw/riscv: Move sifive_uart model to hw/charBin Meng
2020-09-09hw/riscv: Move riscv_htif model to hw/charBin Meng
2020-09-09hw/riscv: Move sifive_plic model to hw/intcBin Meng
2020-09-09hw/riscv: Move sifive_clint model to hw/intcBin Meng
2020-09-09hw/riscv: Move sifive_gpio model to hw/gpioBin Meng
2020-09-09hw/riscv: Move sifive_u_otp model to hw/miscBin Meng
2020-09-09hw/riscv: Move sifive_u_prci model to hw/miscBin Meng
2020-09-09hw/riscv: Move sifive_e_prci model to hw/miscBin Meng
2020-09-09hw/riscv: sifive_u: Connect a DMA controllerBin Meng
2020-09-09hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng
2020-09-09hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng
2020-09-09hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng
2020-09-09hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng
2020-06-19hw/char: Initial commit of Ibex UARTAlistair Francis
2020-06-03riscv: Initial commit of OpenTitan machineAlistair Francis
2020-02-10riscv: virt: Use Goldfish RTC deviceAnup Patel
2019-10-28riscv/virt: Add the PFlash CFI01 deviceAlistair Francis
2019-09-17riscv: sifive_u: Fix broken GEM supportBin Meng
2019-09-17riscv: sifive_e: Drop sifive_mmio_emulate()Bin Meng
2019-03-18kconfig: add CONFIG_MSI_NONBROKENPaolo Bonzini
2019-03-11riscv/Kconfig: enable PCI_DEVICESDavid Abdurachmanov
2019-03-07riscv-softmmu.mak: replace CONFIG_* with Kconfig "select" directivesPaolo Bonzini
2019-03-07kconfig: introduce kconfig filesPaolo Bonzini
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