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path: root/hw/pci-bridge
AgeCommit message (Expand)Author
2024-04-25Merge tag 'hw-misc-20240425' of https://github.com/philmd/qemu into stagingRichard Henderson
2024-04-25hw/cxl/cxl-cdat: Make cxl_doe_cdat_init() return booleanZhao Liu
2024-04-25hw, target: Add ResetType argument to hold and exit phase methodsPeter Maydell
2024-03-13Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ...Peter Maydell
2024-03-12hw/pci-bridge/cxl_upstream: Fix missing ERRP_GUARD() in cxl_usp_realize()Zhao Liu
2024-03-12hw/pci-bridge/pxb-cxl: Drop RAS capability from host bridge.Jonathan Cameron
2024-03-12bulk: Access existing variables initialized to &S->F when availablePhilippe Mathieu-Daudé
2024-03-12hw/pci-bridge/cxl_upstream: Fix missing ERRP_GUARD() in cxl_usp_realize()Zhao Liu
2024-03-09hw/pci-bridge/cxl_upstream: Fix problem with g_steal_pointer()Thomas Huth
2024-02-14hw/cxl: Standardize all references on CXL r3.1 and minor updatesJonathan Cameron
2024-02-14hw/pci-bridge/cxl_upstream: Drop g_malloc() failure handlingJonathan Cameron
2024-01-04Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell
2023-12-31meson: remove CONFIG_ALLPaolo Bonzini
2023-12-30hw/pci-bridge: Constify VMStateRichard Henderson
2023-11-07hw/pci-bridge/cxl_downstream: Set default link width and link speedJonathan Cameron
2023-11-07hw/cxl/mbox: Add Physical Switch Identify command.Jonathan Cameron
2023-11-07hw/pci-bridge/cxl_upstream: Move defintion of device to header.Jonathan Cameron
2023-11-07hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExtJonathan Cameron
2023-10-04hw/pci-bridge/cxl-upstream: Add serial number extended capability supportJonathan Cameron
2023-09-21hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBISDave Jiang
2023-09-20hw/pci: spelling fixesMichael Tokarev
2023-08-03hw/pci-bridge/cxl_upstream.c: Use g_new0() in build_cdat_table()Peter Maydell
2023-06-20meson: Replace softmmu_ss -> system_ssPhilippe Mathieu-Daudé
2023-05-19hw/pci-bridge: make building pcie-to-pci bridge configurableSebastian Ott
2023-05-19hw/cxl: cdat: Fix failure to free buffer in erorr pathsJonathan Cameron
2023-04-24hw/pci-bridge: Make PCIe and CXL PXB Devices inherit from TYPE_PXB_DEVJonathan Cameron
2023-04-24hw/pci-bridge: pci_expander_bridge fix type in pxb_cxl_dev_reset()Jonathan Cameron
2023-03-07hw/pxb-cxl: Support passthrough HDM Decoders unless overriddenJonathan Cameron
2023-03-07hw/pci-bridge/cxl_root_port: Wire up MSIJonathan Cameron
2023-03-07hw/pci-bridge/cxl_root_port: Wire up AERJonathan Cameron
2023-03-02hw/pci-bridge/cxl_downstream: Fix type naming mismatchJonathan Cameron
2023-02-27hw: Move ich9.h to southbridge/Bernhard Beschow
2023-01-28pci: acpi hotplug: rename x-native-hotplug to x-do-not-expose-native-hotplug-capIgor Mammedov
2023-01-28pci_bridge: remove whitespaceIgor Mammedov
2023-01-18bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plxPhilippe Mathieu-Daudé
2023-01-08include/hw/cxl: Move typedef PXBDev to cxl.h, and put it to useMarkus Armbruster
2023-01-08include/hw/pci: Break inclusion loop pci_bridge.h and cxl.hMarkus Armbruster
2022-12-21pci: drop redundant PCIDeviceClass::is_bridge fieldIgor Mammedov
2022-12-21remove DEC 21154 PCI bridgeIgor Mammedov
2022-12-16pci: Convert child classes of TYPE_PCIE_ROOT_PORT to 3-phase resetPeter Maydell
2022-12-16pci: Convert TYPE_PCIE_ROOT_PORT to 3-phase resetPeter Maydell
2022-11-07hw/pci-bridge/cxl-upstream: Add a CDAT table access DOEJonathan Cameron
2022-06-16pci-bridge/cxl_downstream: Add a CXL switch downstream portJonathan Cameron
2022-06-16pci-bridge/cxl_upstream: Add a CXL switch upstream portJonathan Cameron
2022-06-09pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.Jonathan Cameron
2022-06-09hw/cxl: Make the CXL fixed memory window setup a machine parameter.Jonathan Cameron
2022-05-13CXL/cxl_component: Add cxl_get_hb_cstate()Jonathan Cameron
2022-05-13acpi/cxl: Create the CEDT (9.14.1)Ben Widawsky
2022-05-13hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142)Ben Widawsky
2022-05-13hw/cxl/rp: Add a root portBen Widawsky
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