aboutsummaryrefslogtreecommitdiff
path: root/hw/pci-bridge/cxl_upstream.c
AgeCommit message (Expand)Author
2024-11-04hw/pci-bridge/cxl-upstream: Add properties to control link speed and widthJonathan Cameron
2024-09-13hw: Use device_class_set_legacy_reset() instead of opencodingPeter Maydell
2024-09-10qapi/machine: Drop temporary 'prefix'Markus Armbruster
2024-04-25hw/cxl/cxl-cdat: Make cxl_doe_cdat_init() return booleanZhao Liu
2024-03-12hw/pci-bridge/cxl_upstream: Fix missing ERRP_GUARD() in cxl_usp_realize()Zhao Liu
2024-03-09hw/pci-bridge/cxl_upstream: Fix problem with g_steal_pointer()Thomas Huth
2024-02-14hw/cxl: Standardize all references on CXL r3.1 and minor updatesJonathan Cameron
2024-02-14hw/pci-bridge/cxl_upstream: Drop g_malloc() failure handlingJonathan Cameron
2023-11-07hw/pci-bridge/cxl_upstream: Move defintion of device to header.Jonathan Cameron
2023-11-07hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExtJonathan Cameron
2023-10-04hw/pci-bridge/cxl-upstream: Add serial number extended capability supportJonathan Cameron
2023-09-21hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBISDave Jiang
2023-08-03hw/pci-bridge/cxl_upstream.c: Use g_new0() in build_cdat_table()Peter Maydell
2023-05-19hw/cxl: cdat: Fix failure to free buffer in erorr pathsJonathan Cameron
2022-12-21pci: drop redundant PCIDeviceClass::is_bridge fieldIgor Mammedov
2022-11-07hw/pci-bridge/cxl-upstream: Add a CDAT table access DOEJonathan Cameron
2022-06-16pci-bridge/cxl_upstream: Add a CXL switch upstream portJonathan Cameron
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-17 22:53:02 +0000