Age | Commit message (Expand) | Author |
2023-01-06 | hw/intc: sifive_plic: Fix the pending register range check | Bin Meng |
2023-01-06 | hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 | Bin Meng |
2023-01-06 | hw/intc: sifive_plic: Update "num-sources" property default value | Bin Meng |
2023-01-06 | hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in ... | Bin Meng |
2023-01-06 | hw/intc: sifive_plic: Improve robustness of the PLIC config parser | Bin Meng |
2023-01-06 | hw/intc: sifive_plic: Drop PLICMode_H | Bin Meng |
2023-01-06 | hw/intc: sifive_plic: fix out-of-bound access of source_priority array | Jim Shu |
2023-01-06 | hw/intc: sifive_plic: Renumber the S irqs for numa support | Frédéric Pétrot |
2022-10-14 | hw/intc: sifive_plic: change interrupt priority register to WARL field | Jim Shu |
2022-10-14 | hw/intc: sifive_plic: fix hard-coded max priority level | Jim Shu |
2022-07-28 | hw/intc: sifive_plic: Fix multi-socket plic configuraiton | Atish Patra |
2022-06-10 | hw/intc: sifive_plic: Avoid overflowing the addr_config buffer | Alistair Francis |
2022-01-21 | target/riscv: Support start kernel directly by KVM | Yifei Jiang |
2022-01-08 | hw/intc: sifive_plic: Cleanup remaining functions | Alistair Francis |
2022-01-08 | hw/intc: sifive_plic: Cleanup the read function | Alistair Francis |
2022-01-08 | hw/intc: sifive_plic: Cleanup the write function | Alistair Francis |
2022-01-08 | hw/intc: sifive_plic: Add a reset function | Alistair Francis |
2021-10-22 | hw/intc: sifive_plic: Cleanup the irq_request function | Alistair Francis |
2021-10-22 | hw/intc: sifive_plic: Cleanup the realize function | Alistair Francis |
2021-10-22 | hw/intc: sifive_plic: Move the properties | Alistair Francis |
2021-09-21 | hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines | Alistair Francis |
2021-05-02 | Do not include hw/boards.h if it's not really necessary | Thomas Huth |
2021-05-02 | Do not include sysemu/sysemu.h if it's not really necessary | Thomas Huth |
2020-11-03 | target/riscv: Add sifive_plic vmstate | Yifei Jiang |
2020-09-23 | qemu/atomic.h: rename atomic_ to qatomic_ | Stefan Hajnoczi |
2020-09-09 | hw/riscv: Move sifive_plic model to hw/intc | Bin Meng |