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QEMU is a generic and open source machine & userspace emulator and virtualizer
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armv7m_nvic.c
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Author
2024-01-09
hw/intc/armv7m_nvic: add "num-prio-bits" property
Samuel Tardieu
2023-12-29
hw/intc: Constify VMState
Richard Henderson
2023-10-27
target/arm: Move feature test functions to their own header
Peter Maydell
2023-07-25
arm: spelling fixes
Michael Tokarev
2023-02-27
hw/intc/armv7m_nvic: Use QOM cast CPU() macro
Philippe Mathieu-Daudé
2023-02-27
target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled
Fabiano Rosas
2023-02-16
target/arm: Store CPUARMState::nvic as NVICState*
Philippe Mathieu-Daudé
2022-07-18
hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high
Peter Maydell
2021-09-01
arm: Move system PPB container handling to armv7m
Peter Maydell
2021-09-01
arm: Move systick device creation from NVIC to ARMv7M object
Peter Maydell
2021-09-01
arm: Move M-profile RAS register block into its own device
Peter Maydell
2021-07-27
hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
Peter Maydell
2021-07-27
hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
Peter Maydell
2021-07-27
hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts
Peter Maydell
2021-06-15
hw/intc/armv7m_nvic: Remove stale comment
Peter Maydell
2021-05-02
Do not include cpu.h if it's not really necessary
Thomas Huth
2021-01-08
hw/intc/armv7m_nvic: Correct handling of CCR.BFHFNMIGN
Peter Maydell
2020-12-10
hw/intc/armv7m_nvic: Implement read/write for RAS register block
Peter Maydell
2020-12-10
target/arm: Implement M-profile "minimal RAS implementation"
Peter Maydell
2020-12-10
hw/intc/armv7m_nvic: Fix "return from inactive handler" check
Peter Maydell
2020-12-10
hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit
Peter Maydell
2020-12-10
target/arm: Implement v8.1M REVIDR register
Peter Maydell
2020-12-10
hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M
Peter Maydell
2020-12-10
hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault
Peter Maydell
2020-10-01
hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs
Peter Maydell
2020-10-01
target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters
Peter Maydell
2020-09-01
hw: Remove superfluous breaks
Liao Pingfang
2020-08-03
hw/intc/armv7m_nvic: Provide default "reset the system" behaviour for SYSRESE...
Peter Maydell
2020-07-10
error: Eliminate error_propagate() with Coccinelle, part 1
Markus Armbruster
2020-07-10
qdev: Use returned bool to check for qdev_realize() etc. failure
Markus Armbruster
2020-06-15
sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 3
Markus Armbruster
2020-06-15
sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1
Markus Armbruster
2020-03-12
hw/intc/armv7m_nvic: Rebuild hflags on reset
Peter Maydell
2020-02-28
target/arm: Add isar_feature_aa32_vfp_simd
Richard Henderson
2020-02-21
target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks
Peter Maydell
2020-02-21
target/arm: Define an aa32_pmu_8_1 isar feature test function
Peter Maydell
2020-01-24
qdev: set properties with device_class_set_props()
Marc-André Lureau
2019-10-24
target/arm: Rebuild hflags for M-profile NVIC
Richard Henderson
2019-09-03
memory: Access MemoryRegion with endianness
Tony Nguyen
2019-09-03
hw/intc/armv7m_nic: Access MemoryRegion with MemOp
Tony Nguyen
2019-08-16
Include hw/qdev-properties.h less
Markus Armbruster
2019-08-16
Include migration/vmstate.h less
Markus Armbruster
2019-08-16
Include hw/irq.h a lot less
Markus Armbruster
2019-07-04
target/arm: v8M: Check state of exception being returned from
Peter Maydell
2019-07-04
arm v8M: Forcibly clear negative-priority exceptions on deactivate
Peter Maydell
2019-06-12
Include qemu/module.h where needed, drop it from qemu-common.h
Markus Armbruster
2019-05-24
hw/intc/nvic: Use object_initialize_child for correct reference counting
Philippe Mathieu-Daudé
2019-05-23
arm: Remove unnecessary includes of hw/arm/arm.h
Peter Maydell
2019-05-07
hw/intc/armv7m_nvic: Don't enable ARMV7M_EXCP_DEBUG from reset
Peter Maydell
2019-05-07
hw/intc/armv7m_nvic: NS BFAR and BFSR are RAZ/WI if BFHFNMINS == 0
Peter Maydell
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