| Age | Commit message (Expand) | Author |
|---|
| 2023-01-18 | bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx | Philippe Mathieu-Daudé |
| 2022-12-15 | hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement | Luke Starrett |
| 2022-06-08 | Fix 'writeable' typos | Peter Maydell |
| 2022-04-22 | hw/intc/arm_gicv3: Update ID and feature registers for GICv4 | Peter Maydell |
| 2022-04-22 | hw/intc/arm_gicv3: Report correct PIDR0 values for ID registers | Peter Maydell |
| 2022-03-07 | hw/intc/arm_gicv3: Fix missing spaces in error log messages | Peter Maydell |
| 2021-09-13 | hw/intc: GICv3 ITS Feature enablement | Shashi Mallela |
| 2021-09-01 | hw/intc/arm_gicv3: Replace mis-used MEMTX_* constants by booleans | Philippe Mathieu-Daudé |
| 2021-09-01 | hw/intc/arm_gicv3_dist: Rename 64-bit accessors with 'q' suffix | Philippe Mathieu-Daudé |
| 2019-06-17 | hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1 | Peter Maydell |
| 2019-06-17 | hw/intc/arm_gicv3: Fix decoding of ID register range | Peter Maydell |
| 2018-06-22 | hw/intc/arm_gicv3: fix an extra left-shift when reading IPRIORITYR | Amol Surati |
| 2018-01-11 | hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI | Peter Maydell |
| 2016-06-20 | hw/intc/arm_gicv3: Fix compilation with simple trace backend | Peter Maydell |
| 2016-06-17 | hw/intc/arm_gicv3: Implement gicv3_set_irq() | Peter Maydell |
| 2016-06-17 | hw/intc/arm_gicv3: Implement GICv3 distributor registers | Shlomo Pongratz |
