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path: root/hw/intc/arm_gicv3_dist.c
AgeCommit message (Expand)Author
2024-04-25hw/intc/arm_gicv3: Implement GICD_INMIRJinjie Ruan
2024-04-25hw/intc/arm_gicv3: Add has-nmi property to GICv3 deviceJinjie Ruan
2023-01-18bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plxPhilippe Mathieu-Daudé
2022-12-15hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisementLuke Starrett
2022-06-08Fix 'writeable' typosPeter Maydell
2022-04-22hw/intc/arm_gicv3: Update ID and feature registers for GICv4Peter Maydell
2022-04-22hw/intc/arm_gicv3: Report correct PIDR0 values for ID registersPeter Maydell
2022-03-07hw/intc/arm_gicv3: Fix missing spaces in error log messagesPeter Maydell
2021-09-13hw/intc: GICv3 ITS Feature enablementShashi Mallela
2021-09-01hw/intc/arm_gicv3: Replace mis-used MEMTX_* constants by booleansPhilippe Mathieu-Daudé
2021-09-01hw/intc/arm_gicv3_dist: Rename 64-bit accessors with 'q' suffixPhilippe Mathieu-Daudé
2019-06-17hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1Peter Maydell
2019-06-17hw/intc/arm_gicv3: Fix decoding of ID register rangePeter Maydell
2018-06-22hw/intc/arm_gicv3: fix an extra left-shift when reading IPRIORITYRAmol Surati
2018-01-11hw/intc/arm_gicv3: Make reserved register addresses RAZ/WIPeter Maydell
2016-06-20hw/intc/arm_gicv3: Fix compilation with simple trace backendPeter Maydell
2016-06-17hw/intc/arm_gicv3: Implement gicv3_set_irq()Peter Maydell
2016-06-17hw/intc/arm_gicv3: Implement GICv3 distributor registersShlomo Pongratz
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