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2024-09-05hw/arm/sbsa-ref: Don't leak string in sbsa_fdt_add_gic_node()Peter Maydell
In sbsa_fdt_add_gic_node() we g_strdup_printf() two nodename strings, but only free one. Since the string is actually entirely constant and we don't make any use of printf's format-string operations, we can drop the g_strdup_printf() use entirely. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20240822162323.706382-1-peter.maydell@linaro.org
2024-09-05hw/arm/sbsa-ref: Use two-stage SMMUPeter Maydell
Now that our SMMU model supports enabling both stages of translation at once, we can enable this in the sbsa-ref board. Existing guest code that only programs stage 1 and doesn't care about stage 2 should continue to run with the same behaviour, but guests that do want to do nested SMMU configurations can now do so. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Message-id: 20240816161350.3706332-5-peter.maydell@linaro.org
2024-06-21hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machineXiong Yining
Enable CPU cluster support on SbsaQemu platform, so that users can specify a 4-level CPU hierarchy sockets/clusters/cores/threads. And this topology can be passed to the firmware through /cpus/topology Device Tree. Signed-off-by: Xiong Yining <xiongyining1480@phytium.com.cn> Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Message-id: 20240607103825.1295328-2-xiongyining1480@phytium.com.cn Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-06-21hw/arm/sbsa-ref: switch to 1GHz timer frequencyMarcin Juszkiewicz
Updated firmware for QEMU CI is already in merge queue so we can move platform to be future proof. All supported cpus work fine with 1GHz timer frequency when firmware is fresh enough. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Message-id: 20240531093729.220758-2-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30arm/sbsa-ref: move to Neoverse-N2 as defaultMarcin Juszkiewicz
Moving to Neoverse-N2 gives us several cpu features to use for expanding our platform: - branch target identification - pointer authentication - RME for confidential computing - RNG for EFI_PROTOCOL_RNG - SVE being enabled by default We do not go for "max" as default to have stable set of features enabled by default. It is still supported and can be selected with "--cpu" argument. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Message-id: 20240523165353.6547-1-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-30hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM propertyPeter Maydell
Currently the sbsa_gdwt watchdog device hardcodes its frequency at 62.5MHz. In real hardware, this watchdog is supposed to be driven from the system counter, which also drives the CPU generic timers. Newer CPU types (in particular from Armv8.6) should have a CPU generic timer frequency of 1GHz, so we can't leave the watchdog on the old QEMU default of 62.5GHz. Make the frequency a QOM property so it can be set by the board, and have our only board that uses this device set that frequency to the same value it sets the CPU frequency. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240426122913.3427983-4-peter.maydell@linaro.org
2024-04-30hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHzPeter Maydell
Currently QEMU CPUs always run with a generic timer counter frequency of 62.5MHz, but ARMv8.6 CPUs will run at 1GHz. For older versions of the TF-A firmware that sbsa-ref runs, the frequency of the generic timer is hardcoded into the firmware, and so if the CPU actually has a different frequency then timers in the guest will be set incorrectly. The default frequency used by the 'max' CPU is about to change, so make the sbsa-ref board force the CPU frequency to the value which the firmware expects. Newer versions of TF-A will read the frequency from the CPU's CNTFRQ_EL0 register: https://github.com/ARM-software/arm-trusted-firmware/commit/4c77fac98dac0bebc63798aae9101ac865b87148 so in the longer term we could make this board use the 1GHz frequency. We will need to make sure we update the binaries used by our avocado test Aarch64SbsarefMachine.test_sbsaref_alpine_linux_max_pauth_impdef before we can do that. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Message-id: 20240426122913.3427983-3-peter.maydell@linaro.org
2024-02-27hw/arm/sbsa-ref: Simplify init since PCIe is always enabledMarcin Juszkiewicz
There is no point in checking do we have PCIe if first thing after check is adding PCIe card without checking. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240215153311.186772-1-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-27hw/ide: Remove last two uses of ide/internal.h outside of hw/ide/BALATON Zoltan
Remove last two includes of hw/ide/intarnal.h outside of hw/ide and replace them with newly added public header to allow moving internal.h into hw/ide to really stop exposing it. Fixes: a11f439a0e (hw/ide: Stop exposing internal.h to non-IDE files) Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240223142633.933694E6004@zero.eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-27hw/arm/sbsa-ref: Do not open-code ahci_ide_create_devs()Philippe Mathieu-Daudé
Use ahci_ide_create_devs() instead of open-coding it. Not accessing AHCIDevice internals anymore allows to remove "hw/ide/ahci_internal.h" (which isn't really a public header). Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240226080632.9596-2-philmd@linaro.org>
2024-02-15hw/ide/ahci: Move SysBus definitions to 'ahci-sysbus.h'Philippe Mathieu-Daudé
Keep "hw/ide/ahci.h" AHCI-generic. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20240213081201.78951-10-philmd@linaro.org>
2024-02-02hw/arm/sbsa-ref: use pci_init_nic_devices()David Woodhouse
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
2024-01-26target/arm: Move GTimer definitions to new 'gtimer.h' headerPhilippe Mathieu-Daudé
Move Arm A-class Generic Timer definitions to the new "target/arm/gtimer.h" header so units in hw/ which don't need access to ARMCPU internals can use them without having to include the huge "cpu.h". Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-20-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' headerPhilippe Mathieu-Daudé
The ARM_CPU_IRQ/FIQ definitions are used to index the GPIO IRQ created calling qdev_init_gpio_in() in ARMCPU instance_init() handler. To allow non-ARM code to raise interrupt on ARM cores, move they to 'target/arm/cpu-qom.h' which is non-ARM specific and can be included by any hw/ file. File list to include the new header generated using: $ git grep -wEl 'ARM_CPU_(\w*IRQ|FIQ)' Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-18-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26target/arm: Rename arm_cpu_mp_affinityRichard Henderson
Rename to arm_build_mp_affinity. This frees up the name for other usage, and emphasizes that the cpu object is not involved. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-9-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-05hw/arm/sbsa-ref: Check CPU type in machine_run_board_init()Gavin Shan
Set mc->valid_cpu_types so that the user specified CPU type can be validated in machine_run_board_init(). We needn't to do it by ourselves. Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20231204004726.483558-8-gshan@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-11-10hw/arm/sbsa-ref: Use qdev_prop_set_array()Kevin Wolf
Instead of manually setting "foo-len" and "foo[i]" properties, build a QList and use the new qdev_prop_set_array() helper to set the whole array property with a single call. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20231109174240.72376-5-kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2023-10-27target/arm: Implement Neoverse N2 CPU modelPeter Maydell
Implement a model of the Neoverse N2 CPU. This is an Armv9.0-A processor very similar to the Cortex-A710. The differences are: * no FEAT_EVT * FEAT_DGH (data gathering hint) * FEAT_NV (not yet implemented in QEMU) * Statistical Profiling Extension (not implemented in QEMU) * 48 bit physical address range, not 40 * CTR_EL0.DIC = 1 (no explicit icache cleaning needed) * PMCR_EL0.N = 6 (always 6 PMU counters, not 20) Because it has 48-bit physical address support, we can use this CPU in the sbsa-ref board as well as the virt board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20230915185453.1871167-3-peter.maydell@linaro.org
2023-10-19hw/arm/sbsa-ref: use bsa.h for PPI definitionsLeif Lindholm
Use the private peripheral interrupt definitions from bsa.h instead of defining them locally. Refactor to use the INTIDs defined there instead of the PPI# used previously. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Message-id: 20230919090229.188092-4-quic_llindhol@quicinc.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-09-21sbsa-ref: add non-secure EL2 virtual timerMarcin Juszkiewicz
Armv8.1+ cpus have Virtual Host Extension (VHE) which added non-secure EL2 virtual timer. This change adds it to fullfil Arm BSA (Base System Architecture) requirements. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Message-id: 20230913140610.214893-2-marcin.juszkiewicz@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-07-17hw/arm/sbsa-ref: set 'slots' property of xhciYuquan Wang
This extends the slots of xhci to 64, since the default xhci_sysbus just supports one slot. Signed-off-by: Wang Yuquan <wangyuquan1236@phytium.com.cn> Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Message-id: 20230710063750.473510-2-wangyuquan1236@phytium.com.cn Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-07-08hw: Simplify calls to pci_nic_init_nofail()Thomas Huth
pci_nic_init_nofail() calls qemu_find_nic_model(), and this function sets nd->model = g_strdup(default_model) if it has not been initialized yet. So we don't have to set nd->model to the default_nic in the calling sites. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2023-07-06target/arm: Define neoverse-v1Peter Maydell
Now that we have implemented support for FEAT_LSE2, we can define a CPU model for the Neoverse-V1, and enable it for the virt and sbsa-ref boards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230704130647.2842917-3-peter.maydell@linaro.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-04hw/arm/sbsa-ref: use XHCI to replace EHCIYuquan Wang
The current sbsa-ref cannot use EHCI controller which is only able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB. Hence, this uses XHCI to provide a usb controller with 64-bit DMA capablity instead of EHCI. We bump the platform version to 0.3 with this change. Although the hardware at the USB controller address changes, the firmware and Linux can both cope with this -- on an older non-XHCI-aware firmware/kernel setup the probe routine simply fails and the guest proceeds without any USB. (This isn't a loss of functionality, because the old USB controller never worked in the first place.) So we can call this a backwards-compatible change and only bump the minor version. Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn> Message-id: 20230621103847.447508-2-wangyuquan1236@phytium.com.cn [PMM: tweaked commit message; add line to docs about what changes in platform version 0.3] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-06-28hw/arm/sbsa-ref: Include missing 'sysemu/kvm.h' headerPhilippe Mathieu-Daudé
"sysemu/kvm.h" is indirectly pulled in. Explicit its inclusion to avoid when refactoring include/: hw/arm/sbsa-ref.c:693:9: error: implicit declaration of function 'kvm_enabled' is invalid in C99 [-Werror,-Wimplicit-function-declaration] if (kvm_enabled()) { ^ Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230405160454.97436-6-philmd@linaro.org>
2023-06-28hw/intc/arm_gic: Un-inline GIC*/ITS class_name() helpersPhilippe Mathieu-Daudé
"kvm_arm.h" contains external and internal prototype declarations. Files under the hw/ directory should only access the KVM external API. In order to avoid machine / device models to include "kvm_arm.h" simply to get the QOM GIC/ITS class name, un-inline each class name getter to the proper device model file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230405160454.97436-4-philmd@linaro.org>
2023-06-26hw/arm: Validate cluster and NUMA node boundaryGavin Shan
There are two ARM machines where NUMA is aware: 'virt' and 'sbsa-ref'. Both of them are required to follow cluster-NUMA-node boundary. To enable the validation to warn about the irregular configuration where multiple CPUs in one cluster have been associated with different NUMA nodes. Signed-off-by: Gavin Shan <gshan@redhat.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20230509002739.18388-3-gshan@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-06-23hw/arm/sbsa-ref: add ITS support in SBSA GICShashi Mallela
Create ITS as part of SBSA platform GIC initialization. GIC ITS information is in DeviceTree so TF-A can pass it to EDK2. Bumping platform version to 0.2 as this is important hardware change. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Message-id: 20230619170913.517373-2-marcin.juszkiewicz@linaro.org Co-authored-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-05-30hw/arm/sbsa-ref: add GIC node into DTMarcin Juszkiewicz
Let add GIC information into DeviceTree as part of SBSA-REF versioning. Trusted Firmware will read it and provide to next firmware level. Bumps platform version to 0.1 one so we can check is node is present. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-05-26hw/arm: Use MachineClass->default_nic in the sbsa-ref machineThomas Huth
Mark the default NIC via the new MachineClass->default_nic setting so that the machine-defaults code in vl.c can decide whether the default NIC is usable or not (for example when compiling with the "--without-default-devices" configure switch). Message-Id: <20230524082037.1620952-1-thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-05-18sbsa-ref: use Bochs graphics card instead of VGAMarcin Juszkiewicz
Bochs card is normal PCI Express card so it fits better in system with PCI Express bus. VGA is simple legacy PCI card. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Message-id: 20230505120936.1097060-1-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-05-18sbsa-ref: switch default cpu core to Neoverse-N1Marcin Juszkiewicz
The world outside moves to newer and newer cpu cores. Let move SBSA Reference Platform to something newer as well. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Message-id: 20230506183417.1360427-1-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-27hw/ide: Rename ide_create_drive() -> ide_bus_create_drive()Philippe Mathieu-Daudé
ide_create_drive() operates on a IDEBus; rename it as ide_bus_create_drive() to emphasize its first argument is a IDEBus. Mechanical change using: $ sed -i -e 's/ide_create_drive/ide_bus_create_drive/g' \ $(git grep -wl ide_create_drive) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230215112712.23110-12-philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-02-03sbsa-ref: remove cortex-a76 from list of supported cpusMarcin Juszkiewicz
Cortex-A76 supports 40bits of address space. sbsa-ref's memory starts above this limit. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230126114416.2447685-1-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-03hw/arm: Use TYPE_ARM_SMMUV3Richard Henderson
Use the macro instead of two explicit string literals. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20230124232059.4017615-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-09hw/arm: add versioning to sbsa-ref machine DTLeif Lindholm
The sbsa-ref machine is continuously evolving. Some of the changes we want to make in the near future, to align with real components (e.g. the GIC-700), will break compatibility for existing firmware. Introduce two new properties to the DT generated on machine generation: - machine-version-major To be incremented when a platform change makes the machine incompatible with existing firmware. - machine-version-minor To be incremented when functionality is added to the machine without causing incompatibility with existing firmware. to be reset to 0 when machine-version-major is incremented. This versioning scheme is *neither*: - A QEMU versioned machine type; a given version of QEMU will emulate a given version of the platform. - A reflection of level of SBSA (now SystemReady SR) support provided. The version will increment on guest-visible functional changes only, akin to a revision ID register found on a physical platform. These properties are both introduced with the value 0. (Hence, a machine where the DT is lacking these nodes is equivalent to version 0.0.) Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Radoslaw Biernacki <rad@semihalf.com> Cc: Cédric Le Goater <clg@kaod.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-09target/arm: Define neoverse-n1Richard Henderson
Enable the n1 for virt and sbsa board use. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-09target/arm: Define cortex-a76Richard Henderson
Enable the a76 for virt and sbsa board use. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-08hw/arm/boot: Drop nb_cpus field from arm_boot_infoPeter Maydell
We use the arm_boot_info::nb_cpus field in only one place, and that place can easily get the number of CPUs locally rather than relying on the board code to have set the field correctly. (At least one board, xlnx-versal-virt, does not set the field despite having more than one CPU.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Tested-by: Cédric Le Goater <clg@kaod.org> Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20220127154639.2090164-16-peter.maydell@linaro.org
2021-12-15hw/arm: Don't include qemu-common.h unnecessarilyPeter Maydell
A lot of C files in hw/arm include qemu-common.h when they don't need anything from it. Drop the include lines. omap1.c, pxa2xx.c and strongarm.c retain the include because they use it for the prototype of qemu_get_timedate(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-id: 20211129200510.1233037-5-peter.maydell@linaro.org
2021-10-20hw/arm/sbsa-ref: Fixed cpu type error message typo.Shuuichirou Ishii
Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Yanan Wang <wangyanan55@huawei.com> Message-Id: <20211008063604.670699-1-ishii.shuuichir@fujitsu.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-08-25sbsa-ref: Rename SBSA_GWDT enum valueEduardo Habkost
The SBSA_GWDT enum value conflicts with the SBSA_GWDT() QOM type checking helper, preventing us from using a OBJECT_DEFINE* or DEFINE_INSTANCE_CHECKER macro for the SBSA_GWDT() wrapper. If I understand the SBSA 6.0 specification correctly, the signal being connected to IRQ 16 is the WS0 output signal from the Generic Watchdog. Rename the enum value to SBSA_GWDT_WS0 to be more explicit and avoid the name conflict. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-id: 20210806023119.431680-1-ehabkost@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-08-02hw/arm/boot: Report error if there is no fw_cfg device in the machinePeter Maydell
If the user provides both a BIOS/firmware image and also a guest kernel filename, arm_setup_firmware_boot() will pass the kernel image to the firmware via the fw_cfg device. However we weren't checking whether there really was a fw_cfg device present, and if there wasn't we would crash. This crash can be provoked with a command line such as qemu-system-aarch64 -M raspi3 -kernel /dev/null -bios /dev/null -display none It is currently only possible on the raspi3 machine, because unless the machine sets info->firmware_loaded we won't call arm_setup_firmware_boot(), and the only machines which set that are: * virt (has a fw-cfg device) * sbsa-ref (checks itself for kernel_filename && firmware_loaded) * raspi3 (crashes) But this is an unfortunate beartrap to leave for future machine model implementors, so we should handle this situation in boot.c. Check in arm_setup_firmware_boot() whether the fw-cfg device exists before trying to load files into it, and if it doesn't exist then exit with a hopefully helpful error message. Because we now handle this check in a machine-agnostic way, we can remove the check from sbsa-ref. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/503 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210726163351.32086-1-peter.maydell@linaro.org
2021-05-02Do not include exec/address-spaces.h if it's not really necessaryThomas Huth
Stop including exec/address-spaces.h in files that don't need it. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210416171314.2074665-5-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-03-05sbsa-ref: add 'max' to list of allowed cpusMarcin Juszkiewicz
Let add 'max' cpu while work goes on adding newer CPU types than Cortex-A72. This allows us to check SVE etc support. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Acked-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210216150122.3830863-3-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05sbsa-ref: remove cortex-a53 from list of supported cpusMarcin Juszkiewicz
Cortex-A53 supports 40bits of address space. sbsa-ref's memory starts above this limit. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Leif Lindholm <leif@nuviainc.com> Message-id: 20210216150122.3830863-2-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-12-10vl: extract softmmu/datadir.cPaolo Bonzini
Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-12-10arm: remove bios_namePaolo Bonzini
Get the firmware name from the MachineState object. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20201026143028.3034018-4-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-12-10sbsa-ref: allow to use Cortex-A53/57/72 cpusMarcin Juszkiewicz
Trusted Firmware now supports A72 on sbsa-ref by default [1] so enable it for QEMU as well. A53 was already enabled there. 1. https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/7117 Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201120141705.246690-1-marcin.juszkiewicz@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-27hw/arm/sbsa-ref: add SBSA watchdog deviceShashi Mallela
Included the newly implemented SBSA generic watchdog device model into SBSA platform Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20201027015927.29495-3-shashi.mallela@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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