slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2024-06-05	disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs	Alistair Francis
2024-04-08	nanomips: fix warnings with GCC 14	Paolo Bonzini
2024-03-29	disas: Show opcodes for target_disas and monitor_disas	Richard Henderson
2024-03-06	target/riscv: honour show_opcodes when disassembling	Alex Bennée
2024-03-06	disas/hppa: honour show_opcodes	Alex Bennée
2024-03-06	disas: introduce show_opcodes	Alex Bennée
2024-02-11	disas/hppa: Add disassembly for qemu specific instructions	Helge Deller
2024-01-30	disas/riscv: Clean up includes	Peter Maydell
2024-01-10	disas/riscv: Add amocas.[w,d,q] instructions	Rob Bradford
2023-11-24	disas/cris: Pass buffer size to format_dec() to avoid overflow warning	Philippe Mathieu-Daudé
2023-11-17	disas/hppa: Show hexcode of instruction along with disassembly	Helge Deller
2023-11-07	disas/riscv: Replace TABs with space	Max Chou
2023-11-07	disas/riscv: Add support for vector crypto extensions	Max Chou
2023-11-07	disas/riscv: Add rv_codec_vror_vi for vror.vi	Max Chou
2023-11-07	disas/riscv: Add rv_fmt_vd_vs2_uimm format	Max Chou
2023-10-12	disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14	Alvin Chang
2023-09-29	disas/m68k: clean up local variable shadowing	Laurent Vivier
2023-07-19	riscv/disas: Fix disas output of upper immediates	Christoph Müllner
2023-07-10	riscv: Add support for the Zfa extension	Christoph Müllner
2023-07-10	target/riscv: Add disas support for BF16 extensions	Weiwei Li
2023-07-10	disas/riscv: Add support for XThead* instructions	Christoph Müllner
2023-07-10	disas/riscv: Add support for XVentanaCondOps	Christoph Müllner
2023-07-10	disas/riscv: Provide infrastructure for vendor extensions	Christoph Müllner
2023-07-10	disas/riscv: Encapsulate opcode_data into decode	Christoph Müllner
2023-07-10	disas/riscv: Make rv_op_illegal a shared enum value	Christoph Müllner
2023-07-10	disas/riscv: Move types/constants to new header file	Christoph Müllner
2023-06-20	meson: Replace softmmu_ss -> system_ss	Philippe Mathieu-Daudé
2023-06-13	disas/riscv.c: Remove redundant parentheses	Weiwei Li
2023-06-13	disas/riscv.c: Fix lines with over 80 characters	Weiwei Li
2023-06-13	disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions	Weiwei Li
2023-06-13	disas/riscv.c: Support disas for Z*inx extensions	Weiwei Li
2023-06-13	disas/riscv.c: Support disas for Zcm* extensions	Weiwei Li
2023-06-13	target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info	Weiwei Li
2023-05-25	disas/riscv: Decode czero.{eqz,nez}	Richard Henderson
2023-05-11	disas: Move disas.c into the target-independent source set	Thomas Huth
2023-05-11	disas: Move softmmu specific code to separate file	Thomas Huth
2023-05-11	disas: Remove target-specific headers	Richard Henderson
2023-05-11	disas: Remove target_ulong from the interface	Richard Henderson
2023-05-11	disas: Move disas.c to disas/	Richard Henderson
2023-05-05	disas/riscv.c: add disasm support for Zc*	Weiwei Li
2023-03-14	Fix incorrect register name in disassembler for fmv,fabs,fneg instructions	Mikhail Tyutin
2023-03-14	disas/riscv: Fix slli_uw decoding	Ivan Klokov
2023-03-05	disas/riscv Fix ctzw disassemble	Ivan Klokov
2023-02-07	target/riscv: update disas.c for xnor/orn/andn and slli.uw	Philipp Tomsich
2023-01-13	mips: Always include nanomips disassembler	Paolo Bonzini
2022-11-08	disas/nanomips: Tidy read for 48-bit opcodes	Richard Henderson
2022-11-08	disas/nanomips: Split out read_u16	Richard Henderson
2022-11-08	disas/nanomips: Merge insn{1,2,3} into words[3]	Richard Henderson
2022-11-08	disas/nanomips: Move setjmp into nanomips_dis	Richard Henderson
2022-11-08	disas/nanomips: Remove headers already included by "qemu/osdep.h"	Philippe Mathieu-Daudé