slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2024-03-06	target/riscv: honour show_opcodes when disassembling	Alex Bennée
2024-01-10	disas/riscv: Add amocas.[w,d,q] instructions	Rob Bradford
2023-11-07	disas/riscv: Replace TABs with space	Max Chou
2023-11-07	disas/riscv: Add support for vector crypto extensions	Max Chou
2023-11-07	disas/riscv: Add rv_codec_vror_vi for vror.vi	Max Chou
2023-10-12	disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14	Alvin Chang
2023-07-19	riscv/disas: Fix disas output of upper immediates	Christoph Müllner
2023-07-10	riscv: Add support for the Zfa extension	Christoph Müllner
2023-07-10	target/riscv: Add disas support for BF16 extensions	Weiwei Li
2023-07-10	disas/riscv: Add support for XThead* instructions	Christoph Müllner
2023-07-10	disas/riscv: Add support for XVentanaCondOps	Christoph Müllner
2023-07-10	disas/riscv: Provide infrastructure for vendor extensions	Christoph Müllner
2023-07-10	disas/riscv: Encapsulate opcode_data into decode	Christoph Müllner
2023-07-10	disas/riscv: Make rv_op_illegal a shared enum value	Christoph Müllner
2023-07-10	disas/riscv: Move types/constants to new header file	Christoph Müllner
2023-06-13	disas/riscv.c: Remove redundant parentheses	Weiwei Li
2023-06-13	disas/riscv.c: Fix lines with over 80 characters	Weiwei Li
2023-06-13	disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions	Weiwei Li
2023-06-13	disas/riscv.c: Support disas for Z*inx extensions	Weiwei Li
2023-06-13	disas/riscv.c: Support disas for Zcm* extensions	Weiwei Li
2023-06-13	target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info	Weiwei Li
2023-05-25	disas/riscv: Decode czero.{eqz,nez}	Richard Henderson
2023-05-05	disas/riscv.c: add disasm support for Zc*	Weiwei Li
2023-03-14	Fix incorrect register name in disassembler for fmv,fabs,fneg instructions	Mikhail Tyutin
2023-03-14	disas/riscv: Fix slli_uw decoding	Ivan Klokov
2023-03-05	disas/riscv Fix ctzw disassemble	Ivan Klokov
2023-02-07	target/riscv: update disas.c for xnor/orn/andn and slli.uw	Philipp Tomsich
2022-10-14	disas/riscv.c: rvv: Add disas support for vector instructions	Yang Liu
2022-09-27	target/riscv: Remove sideleg and sedeleg	Rahul Pathak
2022-09-07	target/riscv: fix shifts shamt value for rv128c	Frédéric Pétrot
2022-04-29	disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions	Weiwei Li
2022-01-08	target/riscv: setup everything for rv64 to support rv128 execution	Frédéric Pétrot
2021-10-07	disas/riscv: Add Zb[abcs] instructions	Philipp Tomsich
2019-06-27	disas/riscv: Fix `rdinstreth` constraint	Wladimir J. van der Laan
2019-06-27	disas/riscv: Disassemble reserved compressed encodings as illegal	Michael Clark
2019-04-18	disas: Rename include/disas/bfd.h back to include/disas/dis-asm.h	Markus Armbruster
2019-03-19	RISC-V: Remove unnecessary disassembler constraints	Michael Clark
2018-05-06	RISC-V: Fix missing break statement in disassembler	Michael Clark
2018-05-06	RISC-V: Include instruction hex in disassembly	Michael Clark
2018-03-28	RISC-V: Fix incorrect disassembly for addiw	Michael Clark
2018-03-07	RISC-V Disassembler	Michael Clark