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2024-11-04bsd-user: Set TaskState ts_tid for initial threadsJessica Clarke
Currently we only set it on fork. Note: Upstream (blitz) commit also did new threads, but that code isn't in qemu project repo yet. Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Pull-Request: https://github.com/qemu-bsd-user/qemu-bsd-user/pull/52 Reviewed-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Warner Losh <imp@bsdimp.com>
2024-11-04bsd-user/main: Allow setting tb-sizeIlya Leoshkevich
While qemu-system can set tb-size using -accel tcg,tb-size=n, there is no similar knob for qemu-bsd-user. Add one in a way similar to how one-insn-per-tb is already handled. Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Warner Losh <imp@bsdimp.com>
2024-11-04bsd-user/x86_64/target_arch_thread.h: Align stackIlya Leoshkevich
bsd-user qemu-x86_64 almost immediately dies with: qemu: 0x4002201a68: unhandled CPU exception 0xd - aborting on FreeBSD 14.1-RELEASE. This is an instruction that requires alignment: (gdb) x/i 0x4002201a68 0x4002201a68: movaps %xmm0,-0x40(%rbp) and the argument is not aligned: (gdb) p/x env->regs[5] $1 = 0x822443b58 A quick experiment shows that the userspace entry point expects misaligned rsp: (gdb) starti (gdb) p/x $rsp $1 = 0x7fffffffeaa8 Emulate this behavior in bsd-user. [[ applied Richard's suggestion ]] Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Warner Losh <imp@bsdimp.com>
2024-10-02bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCVMark Corbin
Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn' functions for RISC-V architecture, Both functions ensure that the CPU state and user context are properly managed. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Co-authored-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-17-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Implement 'get_mcontext' for RISC-VMark Corbin
Added the 'get_mcontext' function to extract and populate the RISC-V machine context from the CPU state. This function is used to gather the current state of the general-purpose registers and store it in a 'target_mcontext_' structure. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Co-authored-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-16-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Implement RISC-V signal trampoline setup functionsMark Corbin
Added functions for setting up the RISC-V signal trampoline and signal frame: 'set_sigtramp_args()': Configures the RISC-V CPU state with arguments for the signal handler. It sets up the registers with the signal number,pointers to the signal info and user context, the signal handler address, and the signal frame pointer. 'setup_sigframe_arch()': Initializes the signal frame with the current machine context.This function copies the context from the CPU state to the signal frame, preparing it for the signal handler. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Co-authored-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-15-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Define RISC-V signal handling structures and constantsMark Corbin
Added definitions for RISC-V signal handling, including structures and constants for managing signal frames and context Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Co-authored-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-14-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Add generic RISC-V64 target definitionsWarner Losh
Added a generic definition for RISC-V64 target-specific details. Implemented the 'regpairs_aligned' function,which returns 'false' to indicate that register pairs are not aligned in the RISC-V64 ABI. Signed-off-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-13-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Define RISC-V system call structures and constantsMark Corbin
Introduced definitions for the RISC-V system call interface, including the 'target_pt_regs' structure that outlines the register storage layout during a system call. Added constants for hardware machine identifiers. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-12-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Define RISC-V VM parameters and helper functionsMark Corbin
Added definitions for RISC-V VM parameters, including maximum and default sizes for text, data, and stack, as well as address space limits. Implemented helper functions for retrieving and setting specific values in the CPU state, such as stack pointer and return values. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-11-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Add RISC-V thread setup and initialization supportMark Corbin
Implemented functions for setting up and initializing threads in the RISC-V architecture. The 'target_thread_set_upcall' function sets up the stack pointer, program counter, and function argument for new threads. The 'target_thread_init' function initializes thread registers based on the provided image information. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com> Co-authored-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-10-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Implement RISC-V sysarch system call emulationMark Corbin
Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch' system call for the RISC-V architecture. Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that the operation is not supported. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-9-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Add RISC-V signal trampoline setup functionMark Corbin
Implemented the 'setup_sigtramp' function for setting up the signal trampoline code in the RISC-V architecture. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-8-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Define RISC-V register structures and register copyingMark Corbin
Added definitions for RISC-V register structures, including general-purpose registers and floating-point registers, in 'target_arch_reg.h'. Implemented the 'target_copy_regs' function to copy register values from the CPU state to the target register structure, ensuring proper endianness handling using 'tswapreg'. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-7-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Add RISC-V ELF definitions and hardware capability detectionMark Corbin
Introduced RISC-V specific ELF definitions and hardware capability detection. Additionally, a function to retrieve hardware capabilities ('get_elf_hwcap') is implemented, which returns the common bits set in each CPU's ISA strings. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Co-authored-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-6-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Implement RISC-V TLS register setupMark Corbin
Included the prototype for the 'target_cpu_set_tls' function in the 'target_arch.h' header file. This function is responsible for setting the Thread Local Storage (TLS) register for RISC-V architecture. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-5-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Implement RISC-V CPU register cloning and reset functionsMark Corbin
Added functions for cloning CPU registers and resetting the CPU state for RISC-V architecture. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-4-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Add RISC-V CPU execution loop and syscall handlingMark Corbin
Implemented the RISC-V CPU execution loop, including handling various exceptions and system calls. The loop continuously executes CPU instructions,processes exceptions, and handles system calls by invoking FreeBSD syscall handlers. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com> Co-authored-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-3-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Implement RISC-V CPU initialization and main loopMark Corbin
Added the initial implementation for RISC-V CPU initialization and main loop. This includes setting up the general-purpose registers and program counter based on the provided target architecture definitions. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-2-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-08-21bsd-user: Handle short reads in mmap_h_gt_gRichard Henderson
In particular, if an image has a large bss, we can hit EOF before reading all bytes of the mapping. Mirror the similar change to linux-user. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240820050848.165253-3-richard.henderson@linaro.org>
2024-07-24bsd-user: Add target.h for aarch64.Warner Losh
For aarch64, it's a 64-bit API, so there's no pairing of registers for 64-bit values. Signed-off-by: Warner Losh <imp@bsdimp.com>
2024-07-23bsd-user: Define TARGET_SIGSTACK_ALIGN and use it to round stackWarner Losh
Most (all?) targets require stacks to be properly aligned. Rather than a series of ifdefs in bsd-user/signal.h, instead use a manditory #define for all architectures. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-07-23bsd-user: Sync fork_start/fork_end with linux-userJessica Clarke
This reorders some of the calls, deduplicates code between branches and, most importantly, fixes a double end_exclusive call in the parent that will cause exclusive_context_count to go negative. Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Pull-Request: https://github.com/qemu-bsd-user/qemu-bsd-user/pull/52 Reviewed-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-07-23bsd-user: Simplify the implementation of execveDoug Rabson
This removes the logic which prepends the emulator to each call to execve and fexecve. This is not necessary with the existing imgact_binmisc support and it avoids the need to install the emulator binary into jail environments when using 'binmiscctl --pre-open'. Signed-off-by: Doug Rabson <dfr@rabson.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Warner Losh <imp@bsdimp.com> Acked-by: Richard Henderson <richard.henderson@linaro.org>
2024-07-23bsd-user:Add AArch64 improvements and signal handling functionsStacey Son
Added get_ucontext_sigreturn function to check processor state ensuring current execution mode is EL0 and no flags indicating interrupts or exceptions are set. Updated AArch64 code to use CF directly without reading/writing the entire processor state, improving efficiency. Changed FP data structures to use Int128 instead of __uint128_t, leveraging QEMU's generic mechanism for referencing this type. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240707191128.10509-9-itachis@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com>
2024-07-23bsd-user:Add set_mcontext function for ARM AArch64Stacey Son
The function copies register values from the provided target_mcontext_t structure to the CPUARMState registers. Note:FP is unfinished upstream but will be a separate commit coming soon. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240707191128.10509-8-itachis@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com>
2024-07-23bsd-user:Add setup_sigframe_arch function for ARM AArch64Warner Losh
The function utilizes the `get_mcontext` function to retrieve the machine context for the current CPUARMState Signed-off-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240707191128.10509-7-itachis@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com>
2024-07-23bsd-user:Add get_mcontext function for ARM AArch64Stacey Son
function to retrieve machine context,it populates the provided target_mcontext_t structure with information from the CPUARMState registers. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Co-authored-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240707191128.10509-6-itachis@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com>
2024-07-23bsd-user:Add ARM AArch64 signal handling supportStacey Son
Added sigcode setup function for signal trampoline which initializes a sequence of instructions to handle signal returns and exits, copying this code to the target offset. Defined ARM AArch64 specific signal definitions including register indices and sizes, and introduced structures to represent general purpose registers, floating point registers, and machine context. Added function to set up signal handler arguments, populating register values in `CPUARMState` based on the provided signal, signal frame, signal action, and frame address. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Co-authored-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240707191128.10509-5-itachis@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com>
2024-07-23bsd-user:Add ARM AArch64 support and capabilitiesWarner Losh
Added function to access rval2 by accessing the x1 register. Defined ARM AArch64 ELF parameters including mmap and dynamic load addresses. Introduced extensive hardware capability definitions and macros for retrieving hardware capability (hwcap) flags. Implemented function to retrieve ARM AArch64 hardware capabilities using the `GET_FEATURE_ID` macro. Added function to retrieve extended ARM AArch64 hardware capability flags. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Co-authored-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240707191128.10509-4-itachis@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com>
2024-07-23bsd-user:Add AArch64 register handling and related functionsStacey Son
Added header file for managing CPU register states in FreeBSD user mode. Introduced prototypes for setting and getting thread-local storage (TLS). Implemented AArch64 sysarch() system call emulation and a printing function. Added function for setting up thread upcall to add thread support to BSD-USER. Initialized thread's register state during thread setup. Updated ARM AArch64 VM parameter definitions for bsd-user, including address spaces for FreeBSD/arm64 and a function for getting the stack pointer from CPU and setting a return value. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com> Co-authored-by: Sean Bruno <sbruno@freebsd.org> Co-authored-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240707191128.10509-3-itachis@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com>
2024-07-23bsd-user:Add CPU initialization and management functionsStacey Son
Added function to initialize ARM CPU and check if it supports 64-bit mode. Implemented CPU loop function to handle exceptions and emulate execution of instructions. Added function to clone CPU state to create a new thread. Included AArch64 specific CPU functions for bsd-user to set and receive thread-local-storage value from the tpidr_el0 register. Introduced structure for storing CPU register states for BSD-USER. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Co-authored-by: Kyle Evans <kevans@freebsd.org> Co-authored-by: Sean Bruno <sbruno@freebsd.org> Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240707191128.10509-2-itachis@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com>
2024-06-09bsd-user: Catch up to run-time reserved_va mathWarner Losh
Catch up to linux-user's 8f67b9c694d0, 13c13397556a, 2f7828b57293, and 95059f9c313a by Richard Henderson which made reserved_va a run-time calculation, defaulting to nothing except in the case of 64-bit host 32-bit target. Also include the adjustment of the comment heading that work submitted in the same patch stream. Since this is a direct copy, squash it into one patch rather than follow the Linux evolution since breaking this down further at this point doesn't make sense for this "new code". Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-09bsd-user: port linux-user:ff8a8bbc2ad1 for variable page sizesWarner Losh
Bring in Richard Henderson's ff8a8bbc2ad1 to finalize the page size to allow TARGET_PAGE_BITS_VARY. bsd-user's "blitz" fork has aarch64 support, which is now variable page size. Add support for it here, even though it's effectively a nop in upstream qemu. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-06user: Declare get_task_state() once in 'accel/tcg/vcpu-state.h'Philippe Mathieu-Daudé
While each user emulation implentation defines its own TaskState structure, both use the same get_task_state() declaration, in particular in common code (such gdbstub). Declare the method once in "accel/tcg/vcpu-state.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428221450.26460-10-philmd@linaro.org>
2024-05-06user: Forward declare TaskState type definitionPhilippe Mathieu-Daudé
Forward declare TaskState in "qemu/typedefs.h" so we can use it in generic headers like "hw/cpu/core.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428221450.26460-9-philmd@linaro.org>
2024-05-06exec/cpu: Extract page-protection definitions to page-protection.hPhilippe Mathieu-Daudé
Extract page-protection definitions from "exec/cpu-all.h" to "exec/page-protection.h". The list of files requiring the new header was generated using: $ git grep -wE \ 'PAGE_(READ|WRITE|EXEC|RWX|VALID|ANON|RESERVED|TARGET_.|PASSTHROUGH)' Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Nicholas Piggin <npiggin@gmail.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-3-philmd@linaro.org>
2024-05-06exec/cpu: Rename PAGE_BITS macro to PAGE_RWXBALATON Zoltan
This macro can be used to abbreviate PAGE_READ | PAGE_WRITE | PAGE_EXEC for which PAGE_RWX is a better name and renaming it also shows it is not related to TARGET_PAGE_BITS. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240505121008.44A0D4E602D@zero.eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-03user: Move 'thunk.h' from 'exec/user' to 'user'Philippe Mathieu-Daudé
Keep all user emulation headers under the same user/ directory. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428221450.26460-2-philmd@linaro.org>
2024-05-03user: Move 'abitypes.h' from 'exec/user' to 'user'Philippe Mathieu-Daudé
Keep all user emulation headers under the same user/ directory. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240503125202.35667-1-philmd@linaro.org>
2024-04-26exec: Restrict inclusion of 'user/guest-base.h'Philippe Mathieu-Daudé
Declare 'have_guest_base' in "user/guest-base.h". Very few files require this header, so explicitly include it there instead of "exec/cpu-all.h" which is used in many source files. Assert this user-specific header is only included from user emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231211212003.21686-23-philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng>
2024-04-26exec: Move [b]tswapl() declarations to 'exec/user/tswap-target.h'Philippe Mathieu-Daudé
tswapl() and bswaptls() are target-dependent and only used by user emulation. Move their definitions to a new header: "exec/user/tswap-target.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20231212123401.37493-17-philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-04-25Merge tag 'hw-misc-20240425' of https://github.com/philmd/qemu into stagingRichard Henderson
Misc HW patch queue - Script to compare machines compat_props[] (Maksim) - Introduce 'module' CPU topology level (Zhao) - Various cleanups (Thomas, Zhao, Inès, Bernhard) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmYqN3wACgkQ4+MsLN6t # wN4hTw/9FHsItnEkme/864DRPSP7A9mCGa+JfzJmsL8oUb9fBjXXKm+lNchMLu3B # uvzfXB2Ea24yf5vyrldo0XlU3i/4GDvqXTI6YFYqBvitGICauYBu+6n2NZh2Y/Pn # zZCcVo167o0q7dHu2WSrZ6cSUchsF2C80HjuS07QaN2YZ7QMuN1+uqTjCQ/JHQWA # MH4xHh7cXdfCbbv8iNhMWn6sa+Bw/UyfRcc2W6w9cF5Q5cuuTshgDyd0JBOzkM1i # Mcul7TuKrSiLUeeeqfTjwtw3rtbNfkelV3ycgvgECFAlzPSjF5a6d/EGdO2zo3T/ # aFZnQBYrb4U0SzsmfXFHW7cSylIc1Jn2CCuZZBIvdVcu8TGDD5XsgZbGoCfKdWxp # l67qbQJy1Mp3LrRzygJIaxDOfE8fhhRrcIxfK/GoTHaCkqeFRkGjTeiDTVBqAES2 # zs6kUYZyG/xGaa2tsMu+HbtSO5EEqPC2QCdHayY3deW42Kwjj/HFV50Ya8YgYSVp # gEAjTDOle2dDjlkYud+ymTJz7LnGb3G7q0EZRI9DWolx/bu+uZGQqTSRRre4qFQY # SgN576hsFGN4NdM7tyJWiiqD/OC9ZeqUx3gGBtmI52Q6obBCE9hcow0fPs55Tk95 # 1YzPrt/3IoPI5ZptCoA8DFiysQ46OLtpIsQO9YcrpJmxWyLDSr0= # =tm+U # -----END PGP SIGNATURE----- # gpg: Signature made Thu 25 Apr 2024 03:59:08 AM PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] * tag 'hw-misc-20240425' of https://github.com/philmd/qemu: (22 commits) hw/core: Support module-id in numa configuration hw/core: Introduce module-id as the topology subindex hw/core/machine: Support modules in -smp hw/core/machine: Introduce the module as a CPU topology level hw/i386/pc_sysfw: Remove unused parameter from pc_isa_bios_init() hw/misc : Correct 5 spaces indents in stm32l4x5_exti hw/xtensa: Include missing 'exec/cpu-common.h' in 'bootparam.h' hw/elf_ops: Rename elf_ops.h -> elf_ops.h.inc hw/cxl/cxl-cdat: Make cxl_doe_cdat_init() return boolean hw/cxl/cxl-cdat: Make ct3_build_cdat() return boolean hw/cxl/cxl-cdat: Make ct3_load_cdat() return boolean hw: Add a Kconfig switch for the TYPE_CPU_CLUSTER device hw: Fix problem with the A*MPCORE switches in the Kconfig files hw/riscv/virt: Replace sprintf by g_strdup_printf hw/misc/imx: Replace sprintf() by snprintf() hw/misc/applesmc: Simplify DeviceReset handler target/i386: Move APIC related code to cpu-apic.c hw/core: Remove check on NEED_CPU_H in tcg-cpu-ops.h scripts: add script to compare compatibility properties python/qemu/machine: add method to retrieve QEMUMachine::binary field ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-04-25hw/elf_ops: Rename elf_ops.h -> elf_ops.h.incPhilippe Mathieu-Daudé
Since commit 139c1837db ("meson: rename included C source files to .c.inc"), QEMU standard procedure for included C files is to use *.c.inc. Besides, since commit 6a0057aa22 ("docs/devel: make a statement about includes") this is documented in the Coding Style: If you do use template header files they should be named with the ``.c.inc`` or ``.h.inc`` suffix to make it clear they are being included for expansion. Therefore rename "hw/elf_ops.h" as "hw/elf_ops.h.inc". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240424173333.96148-2-philmd@linaro.org>
2024-04-24meson: Make DEBUG_REMAP a meson optionIlya Leoshkevich
Currently DEBUG_REMAP is a macro that needs to be manually #defined to be activated, which makes it hard to have separate build directories dedicated to testing the code with it. Promote it to a meson option. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20240312002402.14344-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-03-13gdbstub: Save target's siginfoGustavo Romero
Save target's siginfo into gdbserver_state so it can be used later, for example, in any stub that requires the target's si_signo and si_code. This change affects only linux-user mode. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240309030901.1726211-4-gustavo.romero@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-03-12user: Prefer fast cpu_env() over slower CPU QOM cast macroPhilippe Mathieu-Daudé
Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Message-ID: <20240129164514.73104-30-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-03-06gdbstub: Call gdbserver_fork() both in parent and in childIlya Leoshkevich
The upcoming follow-fork-mode child support requires post-fork message exchange between the parent and the child. Prepare gdbserver_fork() for this purpose. Rename it to gdbserver_fork_end() to better reflect its purpose. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20240219141628.246823-8-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-9-alex.bennee@linaro.org>
2024-03-06{linux,bsd}-user: Pass pid to gdbserver_fork()Ilya Leoshkevich
The upcoming follow-fork-mode child support requires knowing the child pid. Pass it down. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20240219141628.246823-7-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-8-alex.bennee@linaro.org>
2024-03-06{linux,bsd}-user: Pass pid to fork_end()Ilya Leoshkevich
The upcoming follow-fork-mode child support requires knowing the child pid. Pass it down. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20240219141628.246823-6-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-7-alex.bennee@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2024-11-21 16:10:22 +0000