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2020-09-09hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23Bin Meng
When cadence_gem model was created for Xilinx boards, the PHY address was hard-coded to 23 in the GEM model. Now that we have introduced a property we can use that to tell GEM model what our PHY address is. Change all boards' GEM 'phy-addr' property value to 23, and set the PHY address default value to 0 in the GEM model. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-13-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/net: cadence_gem: Add a new 'phy-addr' propertyBin Meng
At present the PHY address of the PHY connected to GEM is hard-coded to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for all boards. Add a new 'phy-addr' property so that board can specify the PHY address for each GEM instance. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-12-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng
On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA controller to move the 2nd stage bootloader in the system memory. Let's connect a DMA controller to Microchip PolarFire SoC. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-11-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/dma: Add SiFive platform DMA controller emulationBin Meng
Microchip PolarFire SoC integrates a DMA engine that supports: * Independent concurrent DMA transfers using 4 DMA channels * Generation of interrupts on various conditions during execution which is actually an IP reused from the SiFive FU540 chip. This creates a model to support both polling and interrupt modes. Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-10-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng
Microchip PolarFire SoC integrates one Cadence SDHCI controller. On the Icicle Kit board, one eMMC chip and an external SD card connect to this controller depending on different configuration. As QEMU does not support eMMC yet, we just emulate the SD card configuration. To test this, the Hart Software Services (HSS) should choose the SD card configuration: $ cp boards/icicle-kit-es/def_config.sdcard .config $ make BOARD=icicle-kit-es The SD card image can be built from the Yocto BSP at: https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp Note the generated SD card image should be resized before use: $ qemu-img resize /path/to/sdcard.img 4G Launch QEMU with the following command: $ qemu-system-riscv64 -nographic -M microchip-icicle-kit -sd sdcard.img Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-9-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/sd: Add Cadence SDHCI emulationBin Meng
Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible controller. The SDHCI compatible registers start from offset 0x200, which are called Slot Register Set (SRS) in its datasheet. This creates a Cadence SDHCI model built on top of the existing generic SDHCI model. Cadence specific Host Register Set (HRS) is implemented to make guest software happy. Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-8-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng
Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board wires 4 of them out. Let's connect all 5 MMUARTs. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/char: Add Microchip PolarFire SoC MMUART emulationBin Meng
Microchip PolarFire SoC MMUART is ns16550 compatible, with some additional registers. Create a simple MMUART model built on top of the existing ns16550 model. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-6-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng
This is an initial support for Microchip PolarFire SoC Icicle Kit. The Icicle Kit board integrates a PolarFire SoC, with one SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA. For more details about Microchip PolarFire Soc, please see: https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000. The following perepherals are created as an unimplemented device: - Bus Error Uint 0/1/2/3/4 - L2 cache controller - SYSREG - MPUCFG - IOSCBCFG More devices will be added later. The BIOS image used by this machine is hss.bin, aka Hart Software Services, which can be built from: https://github.com/polarfire-soc/hart-software-services To launch this machine: $ qemu-system-riscv64 -nographic -M microchip-icicle-kit The memory is set to 1 GiB by default to match the hardware. A sanity check on ram size is performed in the machine init routine to prompt user to increase the RAM size to > 1 GiB when less than 1 GiB ram is detected. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-5-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09target/riscv: cpu: Set reset vector based on the configured property valueBin Meng
Now that we have the newly introduced 'resetvec' property in the RISC-V CPU and HART, instead of hard-coding the reset vector addr in the CPU's instance_init(), move that to riscv_cpu_realize() based on the configured property value from the RISC-V machines. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/riscv: hart: Add a new 'resetvec' propertyBin Meng
RISC-V machines do not instantiate RISC-V CPUs directly, instead they do that via the hart array. Add a new property for the reset vector address to allow the value to be passed to the CPU, before CPU is realized. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09target/riscv: cpu: Add a new 'resetvec' propertyBin Meng
Currently the reset vector address is hard-coded in a RISC-V CPU's instance_init() routine. In a real world we can have 2 exact same CPUs except for the reset vector address, which is pretty common in the RISC-V core IP licensing business. Normally reset vector address is a configurable parameter. Let's create a 64-bit property to store the reset vector address which covers both 32-bit and 64-bit CPUs. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-2-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09riscv: sifive_test: Allow 16-bit writes to memory regionNathan Chancellor
When shutting down the machine running a mainline Linux kernel, the following error happens: $ build/riscv64-softmmu/qemu-system-riscv64 -bios default -M virt \ -display none -initrd rootfs.cpio -kernel Image -m 512m \ -nodefaults -serial mon:stdio ... Requesting system poweroff [ 4.999630] reboot: Power down sbi_trap_error: hart0: trap handler failed (error -2) sbi_trap_error: hart0: mcause=0x0000000000000007 mtval=0x0000000000100000 sbi_trap_error: hart0: mepc=0x000000008000d4cc mstatus=0x0000000000001822 sbi_trap_error: hart0: ra=0x000000008000999e sp=0x0000000080015c78 sbi_trap_error: hart0: gp=0xffffffe000e76610 tp=0xffffffe0081b89c0 sbi_trap_error: hart0: s0=0x0000000080015c88 s1=0x0000000000000040 sbi_trap_error: hart0: a0=0x0000000000000000 a1=0x0000000080004024 sbi_trap_error: hart0: a2=0x0000000080004024 a3=0x0000000080004024 sbi_trap_error: hart0: a4=0x0000000000100000 a5=0x0000000000005555 sbi_trap_error: hart0: a6=0x0000000000004024 a7=0x0000000080011158 sbi_trap_error: hart0: s2=0x0000000000000000 s3=0x0000000080016000 sbi_trap_error: hart0: s4=0x0000000000000000 s5=0x0000000000000000 sbi_trap_error: hart0: s6=0x0000000000000001 s7=0x0000000000000000 sbi_trap_error: hart0: s8=0x0000000000000000 s9=0x0000000000000000 sbi_trap_error: hart0: s10=0x0000000000000000 s11=0x0000000000000008 sbi_trap_error: hart0: t0=0x0000000000000000 t1=0x0000000000000000 sbi_trap_error: hart0: t2=0x0000000000000000 t3=0x0000000000000000 sbi_trap_error: hart0: t4=0x0000000000000000 t5=0x0000000000000000 sbi_trap_error: hart0: t6=0x0000000000000000 The kernel does a 16-bit write when powering off the machine, which was allowed before commit 5d971f9e67 ("memory: Revert "memory: accept mismatching sizes in memory_region_access_valid""). Make min_access_size match reality so that the machine can shut down properly now. Cc: qemu-stable@nongnu.org Fixes: 88a07990fa ("SiFive RISC-V Test Finisher") Fixes: 5d971f9e67 ("memory: Revert "memory: accept mismatching sizes in memory_region_access_valid"") Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200901055822.2721209-1-natechancellor@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang
When the cause number is equal to or greater than 23, print "(unknown)" in trace_riscv_trap. The max valid number of riscv_excp_names is 23, so the last excpetion "guest_store_page_fault" can not be printed. In addition, the current check of cause is invalid for riscv_intr_names. So introduce riscv_cpu_get_trap_name to get the trap cause name. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200814035819.1214-1-jiangyifei@huawei.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-08Merge remote-tracking branch ↵Peter Maydell
'remotes/kraxel/tags/sirius/ipxe-20200908-pull-request' into staging ipxe: update to aug 2020 snapshot. # gpg: Signature made Tue 08 Sep 2020 07:09:26 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/sirius/ipxe-20200908-pull-request: ipxe: update binaries ipxe: drop ia32 efi roms ipxe: update submodule Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-08Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2020-09-08' into ↵Peter Maydell
staging QAPI patches patches for 2020-09-08 # gpg: Signature made Tue 08 Sep 2020 07:06:52 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-qapi-2020-09-08: qapi/block-core.json: Fix nbd-server-start docs qapi: Fix indentation, again qapi/migration.json: Fix indentation qapi: Make section headings start a new doc comment block qapi: Reject section markup in definition documentation Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-08Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.2-20200908' ↵Peter Maydell
into staging ppc patch queue 2020-09-08 This supersedes ppc-for-5.2-20200904, it fixes a couple of bugs in that PR and adds a few extra patches. Next pull request for qemu-5.2. The biggest thing here is the generalization of ARM's start-powered-off machine property to all targets. This can fix a number of odd little edge cases where KVM could run vcpus before they were properly initialized. This does include changes to a number of files that aren't normally in my purview. There are suitable Acked-by lines and Peter requested this come in via my tree, since the most pressing requirement for it is in pseries machines with the POWER secure virtual machine facility. In addition we have: * Daniel Barboza's rework and clean up of pseries machine NUMA handling * Correction to behaviour of the nvdimm= generic machine property on pseries * An optimization to the allocation of XIVE interrupts on KVM * Some fixes for confused behaviour with kernel_irqchip when both XICS and XIVE are in play * Add HIOMAP comamnd to pnv flash * Properly advertise the fact that spapr_vscsi doesn't handle hotplugged disks * Some assorted minor enhancements # gpg: Signature made Tue 08 Sep 2020 06:19:34 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-5.2-20200908: (33 commits) spapr_numa: use spapr_numa_get_vcpu_assoc() in home_node hcall spapr_numa: create a vcpu associativity helper spapr: move h_home_node_associativity to spapr_numa.c spapr_numa: move NVLink2 associativity handling to spapr_numa.c spapr, spapr_numa: move lookup-arrays handling to spapr_numa.c spapr, spapr_numa: handle vcpu ibm,associativity spapr: introduce SpaprMachineState::numa_assoc_array ppc/spapr_nvdimm: turn spapr_dt_nvdimm() static ppc: introducing spapr_numa.c NUMA code helper hw/ppc/ppc4xx_pci: Replace pointless warning by assert() hw/ppc/ppc4xx_pci: Use ARRAY_SIZE() instead of magic value target/s390x: Use start-powered-off CPUState property sparc/sun4m: Use start-powered-off CPUState property sparc/sun4m: Don't set cs->halted = 0 in main_cpu_reset() mips/cps: Use start-powered-off CPUState property ppc/e500: Use start-powered-off CPUState property ppc/spapr: Use start-powered-off CPUState property target/arm: Move setting of CPU halted state to generic code target/arm: Move start-powered-off property to generic CPUState ppc/spapr_nvdimm: do not enable support with 'nvdimm=off' ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-08Merge remote-tracking branch 'remotes/rth/tags/pull-mb-20200907-2' into stagingPeter Maydell
Use lookup_and_goto_tb. Cleanup and fill in VMStateDescription. # gpg: Signature made Mon 07 Sep 2020 21:01:55 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-mb-20200907-2: configure: Do not set TARGET_ABI32 for microblaze target/microblaze: Put MicroBlazeCPUConfig into DisasContext target/microblaze: Fill in VMStateDescription for cpu target/microblaze: Move mmu parameters to MicroBlazeCPUConfig target/microblaze: Treat pvr_regs as constant target/microblaze: Move pvr regs to MicroBlazeCPUConfig target/microblaze: Reorg MicroBlazeCPUConfig to minimize holes target/microblaze: Split out MicroBlazeCPUConfig target/microblaze: Diagnose invalid insns in delay slots target/microblaze: Use tcg_gen_lookup_and_goto_ptr target/microblaze: Force rtid, rted, rtbd to exit target/microblaze: Handle DISAS_EXIT_NEXT in delay slot target/microblaze: Replace cpustate_changed with DISAS_EXIT_NEXT target/microblaze: Introduce DISAS_EXIT_NEXT, DISAS_EXIT_JUMP target/microblaze: Rename DISAS_UPDATE to DISAS_EXIT target/microblaze: Rename mmu structs target/microblaze: Cleanup mb_cpu_do_interrupt target/microblaze: Renumber D_FLAG Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-08Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ↵Peter Maydell
staging meson related: * convert unit tests * bugfixes for mtest2make * miscellaneous bugfixes * dead code removal and configure cleanups * oss-fuzz fixes * msys fixes # gpg: Signature made Tue 08 Sep 2020 10:43:27 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini-gitlab/tags/for-upstream: (45 commits) docs: update build system documentation meson: remove linkage of sdl to baum meson: Convert undefsym.sh to undefsym.py fuzz: Add support for custom fuzzing library meson: specify fuzz linker script as a project arg oss-fuzz: fix rpath configure: update dtc submodule docs: suggest Meson replacements for various configure functions configure: drop dead variables and functions configure: do not include dependency flags in QEMU_CFLAGS and LIBS meson: get opengl compilation flags from OPENGL_CFLAGS meson: get glib compilation flags from GLIB_CFLAGS configure: do not look for install(1) configure: remove unnecessary libm test configure: move -ldl test to meson meson: keep all compiler flags detection together configure: move disassembler configuration to meson Makefile: inline the relevant parts of rules.mak Makefile: remove dead variables and includes meson: compute config_all_devices directly ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-08docs: update build system documentationPaolo Bonzini
Most of the Makefile bits are obsolete and can be removed. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: remove linkage of sdl to baumBruce Rogers
Ever since commit 537fe2d63f744e7c96ff45b60d09486a81958e06 there has been a 'linkage' to sdl for compiling baum.c. Originally it had to do with including sdl cflags for any file including sdl headers. There is no longer any such need for baum.c, but the association has persisted in the make system, and with the switch to meson it has now become a hard requirement, which now causes chardev-baum.so to not be produced if sdl is not configured. Remove this bogus linkage. Signed-off-by: Bruce Rogers <brogers@suse.com> Message-Id: <20200903152933.97838-1-brogers@suse.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: Convert undefsym.sh to undefsym.pyYonggang Luo
Shell scripts are not easily invoked from the build process on MSYS, so convert undefsym.sh to a python script. Signed-off-by: Yonggang Luo <luoyonggang@gmail.com> Message-Id: <20200902170054.810-3-luoyonggang@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08fuzz: Add support for custom fuzzing libraryAlexander Bulekov
On oss-fuzz, we must use the LIB_FUZZING_ENGINE and CFLAGS environment variables, rather than -fsanitize=fuzzer. With this change, when LIB_FUZZING_ENGINE is set, the --enable-fuzzing configure option will use that environment variable during the linking stage, rather than -fsanitize=fuzzer Signed-off-by: Alexander Bulekov <alxndr@bu.edu> Message-Id: <20200902173652.307222-3-alxndr@bu.edu> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: specify fuzz linker script as a project argAlexander Bulekov
With this change, the fuzzer-linker script should be specified outside any --start-group/--end-group pairs. We need this on oss-fuzz, where partially applying the linker-script results in a linker failure Signed-off-by: Alexander Bulekov <alxndr@bu.edu> Message-Id: <20200902173652.307222-2-alxndr@bu.edu> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08oss-fuzz: fix rpathAlexander Bulekov
Prior to this change, readelf -d build/out/qemu/qemu-fuzz-i386-target-virtio-net-slirp ... 0x000000000000000f (RPATH) Library rpath: ['$$ORIGIN/lib':$ORIGIN/migration:$ORIGIN/] As of 1a4db552d8 ("ninjatool: quote dollars in variables"), we don't need to manually double the dollars. Also, remove the single-quotes as they are copied into the rpath. After this change: 0x000000000000000f (RPATH) Library rpath: [$ORIGIN/lib:$ORIGIN/migration:$ORIGIN/] Signed-off-by: Alexander Bulekov <alxndr@bu.edu> Message-Id: <20200902142657.112879-3-alxndr@bu.edu> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08configure: update dtc submoduleYonggang Luo
Update the dtc submodule in configure already and symlink dtc after git submodule update, because on win32 symlinks to non-existing folders are forbidden. Signed-off-by: Yonggang Luo <luoyonggang@gmail.com> Message-Id: <20200902170054.810-2-luoyonggang@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08docs: suggest Meson replacements for various configure functionsPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08configure: drop dead variables and functionsPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08configure: do not include dependency flags in QEMU_CFLAGS and LIBSPaolo Bonzini
All Meson executables should specify their dependencies explicitly, either directly or indirectly via declare_dependency. Makefiles instead did not propagate dependencies correctly from static libraries, for example. Therefore, flags for dependencies need not be included in QEMU_CFLAGS. LIBS is not used at all, so drop that one as well. In a few cases the dependencies were not yet specified, so add them. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: get opengl compilation flags from OPENGL_CFLAGSPaolo Bonzini
The opengl compilation flags were added to QEMU_CFLAGS. We do not want them to be added to all compilation commands, so export them also via OPENGL_CFLAGS rather than via QEMU_CFLAGS. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: get glib compilation flags from GLIB_CFLAGSPaolo Bonzini
The glib compilation flags were added to QEMU_CFLAGS. While we still want them to be added to all compilation commands (at least for now), do that via GLIB_CFLAGS rather than via QEMU_CFLAGS. This shows that glib is a special case and makes it clearer that QEMU_CFLAGS is only about compiler commands and not dependencies. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08configure: do not look for install(1)Paolo Bonzini
It is not used anymore, so there is no Solaris-specific check to perform. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08configure: remove unnecessary libm testPaolo Bonzini
The same test is already performed by meson.build. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08configure: move -ldl test to mesonPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: keep all compiler flags detection togetherPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08configure: move disassembler configuration to mesonPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08Makefile: inline the relevant parts of rules.makPaolo Bonzini
Most of rules.mak is not used anymore, just inline what's needed. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08Makefile: remove dead variables and includesPaolo Bonzini
Makefile.objs, the .d files and various CONFIG_* symbols are not used anymore by the Make side of the build; they are only processed by Meson. We can delete them. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: compute config_all_devices directlyPaolo Bonzini
There is no need anymore to produce config-all-devices.mak, compute the resulting dictionary directly instead of going through grepy.sh. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08configure: remove dead code for in-tree buildsPaolo Bonzini
The $pwd_is_source_path variable is never "y", since configure re-executes itself from a build directory. Remove code that will never run. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: convert migration/initrd-stressMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200828110734.1638685-17-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: fix migration/stress compilation with glibc>=2.30Marc-André Lureau
gettid() was introduced with glibc 2.30. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200828110734.1638685-16-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08tests/migration/stress: remove unused exit_successMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200828110734.1638685-15-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: convert the speed testsPaolo Bonzini
Use meson benchmark() for them, adjust mtest2make.py for that. A new target "make bench" can be used to run all benchmarks. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200828110734.1638685-14-marcandre.lureau@redhat.com> [Rewrite mtest2make part. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08tests: do not print benchmark output to stdoutMarc-André Lureau
As this makes the TAP output invalid. Use g_test_message(). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200828110734.1638685-13-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: convert atomic*-benchMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200828110734.1638685-11-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: convert vhost-user-bridgeMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200828110734.1638685-10-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: remove old socket_scm_helper ruleMarc-André Lureau
It was covered already in commit d3ca592b3c10 ("meson: convert check-block") Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200828110734.1638685-9-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: move keyutils dependency checkMarc-André Lureau
Since there is not minimum version specified, and it's a test-only dependency, it's fair to depend on a version that ships with a .pc I suppose. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200828110734.1638685-8-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: convert the unit testsMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200828110734.1638685-7-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-02 20:29:35 +0000