diff options
| author | Bin Meng <bin.meng@windriver.com> | 2020-09-01 09:39:07 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-09-09 15:54:18 -0700 |
| commit | dfc388797cc413072e58a8f9a831633f29212448 (patch) | |
| tree | 5f724d555e92eacfda103e7eefd48265a73bb0b7 | |
| parent | 64ac13633fd416541ea00ff4ae973489bdc33f7a (diff) | |
hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
When cadence_gem model was created for Xilinx boards, the PHY address
was hard-coded to 23 in the GEM model. Now that we have introduced a
property we can use that to tell GEM model what our PHY address is.
Change all boards' GEM 'phy-addr' property value to 23, and set the
PHY address default value to 0 in the GEM model.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-13-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | hw/arm/xilinx_zynq.c | 1 | ||||
| -rw-r--r-- | hw/arm/xlnx-versal.c | 1 | ||||
| -rw-r--r-- | hw/arm/xlnx-zynqmp.c | 2 | ||||
| -rw-r--r-- | hw/net/cadence_gem.c | 6 |
4 files changed, 7 insertions, 3 deletions
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 969ef0727c..9ffcc5606f 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -119,6 +119,7 @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) qemu_check_nic_model(nd, TYPE_CADENCE_GEM); qdev_set_nic_properties(dev, nd); } + object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); s = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); sysbus_mmio_map(s, 0, base); diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index e3aa4bd1e5..12ba6c4eba 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -165,6 +165,7 @@ static void versal_create_gems(Versal *s, qemu_irq *pic) qemu_check_nic_model(nd, "cadence_gem"); qdev_set_nic_properties(dev, nd); } + object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); object_property_set_int(OBJECT(dev), "num-priority-queues", 2, &error_abort); object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps), diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index c435b9d52a..7885bb1774 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -460,6 +460,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) } object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION, &error_abort); + object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23, + &error_abort); object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2, &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) { diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index d80096bbe8..7a534691f1 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -250,7 +250,7 @@ #define GEM_PHYMNTNC_REG_SHIFT 18 /* Marvell PHY definitions */ -#define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */ +#define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */ #define PHY_REG_CONTROL 0 #define PHY_REG_STATUS 1 @@ -1446,7 +1446,7 @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) uint32_t phy_addr, reg_num; phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; - if (phy_addr == s->phy_addr || phy_addr == 0) { + if (phy_addr == s->phy_addr) { reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; retval &= 0xFFFF0000; retval |= gem_phy_read(s, reg_num); @@ -1569,7 +1569,7 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val, uint32_t phy_addr, reg_num; phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; - if (phy_addr == s->phy_addr || phy_addr == 0) { + if (phy_addr == s->phy_addr) { reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; gem_phy_write(s, reg_num, val); } |