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-rw-r--r--target/arm/cpu.c2
-rw-r--r--target/i386/cpu.c4
-rw-r--r--target/microblaze/cpu.c2
-rw-r--r--target/nios2/cpu.c2
-rw-r--r--target/ppc/translate_init.inc.c10
-rw-r--r--target/riscv/cpu.c2
-rw-r--r--target/s390x/cpu.c2
-rw-r--r--target/sparc/cpu.c2
8 files changed, 13 insertions, 13 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index d161da83eb..17cefaa43d 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2693,8 +2693,8 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
device_class_set_parent_realize(dc, arm_cpu_realizefn,
&acc->parent_realize);
- dc->props = arm_cpu_properties;
+ device_class_set_props(dc, arm_cpu_properties);
cpu_class_set_parent_reset(cc, arm_cpu_reset, &acc->parent_reset);
cc->class_by_name = arm_cpu_class_by_name;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ffe5de0f82..5fa6acc34f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4144,7 +4144,7 @@ static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
xcc->model_description =
"Enables all features supported by the accelerator in the current host";
- dc->props = max_x86_cpu_properties;
+ device_class_set_props(dc, max_x86_cpu_properties);
}
static void max_x86_cpu_initfn(Object *obj)
@@ -7161,7 +7161,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
&xcc->parent_realize);
device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
&xcc->parent_unrealize);
- dc->props = x86_cpu_properties;
+ device_class_set_props(dc, x86_cpu_properties);
cpu_class_set_parent_reset(cc, x86_cpu_reset, &xcc->parent_reset);
cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 71d88f603b..8c90110e52 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -308,7 +308,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
#endif
dc->vmsd = &vmstate_mb_cpu;
- dc->props = mb_properties;
+ device_class_set_props(dc, mb_properties);
cc->gdb_num_core_regs = 32 + 5;
cc->disas_set_info = mb_disas_set_info;
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index bbdbc0c6fb..1c0c855a6f 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -187,7 +187,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
device_class_set_parent_realize(dc, nios2_cpu_realizefn,
&ncc->parent_realize);
- dc->props = nios2_properties;
+ device_class_set_props(dc, nios2_properties);
cpu_class_set_parent_reset(cc, nios2_cpu_reset, &ncc->parent_reset);
cc->class_by_name = nios2_cpu_class_by_name;
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 5ffd07c36a..2d3efad233 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -8599,7 +8599,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
dc->fw_name = "PowerPC,POWER7";
dc->desc = "POWER7";
- dc->props = powerpc_servercpu_properties;
+ device_class_set_props(dc, powerpc_servercpu_properties);
pcc->pvr_match = ppc_pvr_match_power7;
pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
@@ -8764,7 +8764,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
dc->fw_name = "PowerPC,POWER8";
dc->desc = "POWER8";
- dc->props = powerpc_servercpu_properties;
+ device_class_set_props(dc, powerpc_servercpu_properties);
pcc->pvr_match = ppc_pvr_match_power8;
pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
@@ -8976,7 +8976,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
dc->fw_name = "PowerPC,POWER9";
dc->desc = "POWER9";
- dc->props = powerpc_servercpu_properties;
+ device_class_set_props(dc, powerpc_servercpu_properties);
pcc->pvr_match = ppc_pvr_match_power9;
pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
@@ -9186,7 +9186,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
dc->fw_name = "PowerPC,POWER10";
dc->desc = "POWER10";
- dc->props = powerpc_servercpu_properties;
+ device_class_set_props(dc, powerpc_servercpu_properties);
pcc->pvr_match = ppc_pvr_match_power10;
pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
PCR_COMPAT_3_00;
@@ -10871,7 +10871,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
&pcc->parent_unrealize);
pcc->pvr_match = ppc_pvr_match_default;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
- dc->props = ppc_cpu_properties;
+ device_class_set_props(dc, ppc_cpu_properties);
cpu_class_set_parent_reset(cc, ppc_cpu_reset, &pcc->parent_reset);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d6f1872728..8c86ebc109 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -492,7 +492,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
#endif
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
- dc->props = riscv_cpu_properties;
+ device_class_set_props(dc, riscv_cpu_properties);
}
char *riscv_isa_string(RISCVCPU *cpu)
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index ca487f5fdd..cf84d307c6 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -453,7 +453,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
device_class_set_parent_realize(dc, s390_cpu_realizefn,
&scc->parent_realize);
- dc->props = s390x_cpu_properties;
+ device_class_set_props(dc, s390x_cpu_properties);
dc->user_creatable = true;
cpu_class_set_parent_reset(cc, s390_cpu_reset_full, &scc->parent_reset);
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 9c306e5271..eeaecbd8d6 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -857,7 +857,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
device_class_set_parent_realize(dc, sparc_cpu_realizefn,
&scc->parent_realize);
- dc->props = sparc_cpu_properties;
+ device_class_set_props(dc, sparc_cpu_properties);
cpu_class_set_parent_reset(cc, sparc_cpu_reset, &scc->parent_reset);
generated by cgit v1.2.3 (git 2.26.2) at 2024-11-22 08:57:40 +0000